A method and apparatus for forming a super-lattice structure on a substrate is described herein. The super-lattice structure includes a plurality of silicon-germanium layers and a plurality of silicon layers disposed in a stacked pattern. The methods described herein produce a super-lattice structure with transition width of less than about 1.4 nm between each of the silicon-germanium layers and an adjacent silicon layer. The methods described herein include flowing one or a combination of a silicon containing gas, a germanium containing gas, and a halogenated species.

A flash memory device includes a substrate, a semiconductor quantum well layer, a semiconductor spacer, a semiconductor channel layer, a gate structure, and source/drain regions. The semiconductor quantum well layer is formed of a first semiconductor material and is disposed over the substrate. The semiconductor spacer is formed of a second semiconductor material and is disposed over the first semiconductor channel layer. The semiconductor channel layer is formed of the first semiconductor material and is disposed over the semiconductor spacer. Thea gate structure is over the second semiconductor channel layer. The source/drain regions are over the substrate and are on opposite sides of the gate structure.

A stacked, high-blocking III-V semiconductor power diode having a first metallic terminal contact layer, formed at least in regions, and a highly doped semiconductor contact region of a first conductivity type and a first lattice constant. A drift layer of a second conductivity type and having a first lattice constant is furthermore provided. A semiconductor contact layer of a second conductivity, which includes an upper side and an underside, and a second metallic terminal contact layer are formed, and the second metallic terminal contact layer being integrally connected to the underside of the semiconductor contact layer, and the semiconductor contact layer having a second lattice constant at least on the underside, and the second lattice constant being the lattice constant of InP, and the drift layer and the highly doped semiconductor contact region each comprising an InGaAs compound or being made up of InGaAs.

A qubit array reparation system includes a reservoir of ultra-cold particle, a detector that determines whether or not qubit sites of a qubit array include respective qubit particles, and a transport system for transporting an ultra-cold particle to a first qubit array site that has been determined by the probe system to not include a qubit particle so that the ultra-cold particle can serve as a qubit particle for the first qubit array site. A qubit array reparation process includes maintaining a reservoir of ultra-cold particles, determining whether or not qubit-array sites contain respective qubit particles, each qubit particle having a respective superposition state, and, in response to a determination that a first qubit site does not contain a respective qubit particle, transporting an ultracold particle to the first qubit site to serve as a qubit particle contained by the first qubit site.

A qubit array reparation system includes a reservoir of ultra-cold particle, a detector that determines whether or not qubit sites of a qubit array include respective qubit particles, and a transport system for transporting an ultra-cold particle to a first qubit array site that has been determined by the probe system to not include a qubit particle so that the ultra-cold particle can serve as a qubit particle for the first qubit array site. A qubit array reparation process includes maintaining a reservoir of ultra-cold particles, determining whether or not qubit-array sites contain respective qubit particles, each qubit particle having a respective superposition state, and, in response to a determination that a first qubit site does not contain a respective qubit particle, transporting an ultracold particle to the first qubit site to serve as a qubit particle contained by the first qubit site.

A power semiconductor device includes an SiC semiconductor layer, a plurality of well regions disposed in the semiconductor layer such that two adjacent well regions at least partially make contact with each other, a plurality of source regions on the plurality of well regions in the semiconductor layer, a drift region in a first conductive type, a plurality of trenches recessed into the semiconductor layer from the surface of the semiconductor layer, a gate insulating layer on an inner wall of each trench, a gate electrode layer disposed on the gate insulating layer and including a first part disposed in each trench and a second part on the semiconductor layer, and a pillar region positioned under the plurality of well regions to make contact with the drift region and the plurality of well regions in the semiconductor layer, and having a second conductive type.

There is provided an aluminum nitride laminate member including: a sapphire substrate having a base surface on which bumps are distributed periodically, each bump having a height of smaller than or equal to 500 nm; and an aluminum nitride layer grown on the base surface and having a flat surface, there being substantially no voids in the aluminum nitride layer.

An epitaxy substrate and a method of manufacturing the same are provided. The epitaxy substrate includes a silicon substrate and a silicon carbide layer. The silicon substrate has a first surface and a second surface opposite to each other, and the first surface is an epitaxy surface. The silicon carbide layer is located in the silicon substrate, and a distance between the silicon carbide layer and the first surface is between 100 angstroms (Å) and 500 angstroms.

An exemplary embodiment of the present disclosure provides a method of fabricating a semiconductor device, comprising: providing a substrate, the substate comprising a base layer and two or more planar heteroepitaxial layers deposited on the base layer, the two or more heteroepitaxial layers comprising a first epitaxial layer having a first lattice constant and a second epitaxial layer having a second lattice constant different than the first lattice constant; etching the substrate to form one or more mesas; and depositing one or more non-planar overgrowth layers on the etched substrate.

The present disclosure relates to a micro light emitting diode (LED) display device including a substrate having a plurality of thin film transistors thereon; a plurality of micro light emitting devices (LEDs) on an upper surface of the substrate, the micro LEDs each having a protecting film provided with a first contact hole to expose a portion of an upper surface of a corresponding micro LED; at least one insulating layer covering the micro LED, the insulating layer provided with a second contact hole to expose a portion of the upper surface of the corresponding micro LED; and a connection electrode in the first contact hole and the second contact hole configured to transfer signals to the micro LED, wherein the first contact hole is larger than the second contact hole.