For example, a pin diode is constituted by a silicon carbide epitaxial substrate in which silicon carbide epitaxial layers constituting an n-type buffer region, an n.sup.-type drift region, and a p.sup.++-type anode region are sequentially formed by epitaxial growth on a front surface of an n.sup.+-type silicon carbide substrate. The n.sup.-type drift region has an n-type impurity concentration is, for example, about 110.sup.14/cm.sup.3 to 110.sup.16/cm.sup.3. The n.sup.-type drift region has a boron concentration that is substantially lower than an n-type impurity concentration of the n.sup.-type drift region and that, for example, is about 110.sup.14/cm.sup.3 or less. During epitaxial growth of the n.sup.-type drift region, automatic doping of boron to the n.sup.-type drift region is suppressed, whereby the boron concentration of the n.sup.-type drift region is reduced and the n.sup.-type drift region in which no traps are present is formed.

For example, a pin diode is constituted by a silicon carbide epitaxial substrate in which silicon carbide epitaxial layers constituting an n-type buffer region, an n.sup.-type drift region, and a p.sup.++-type anode region are sequentially formed by epitaxial growth on a front surface of an n.sup.+-type silicon carbide substrate. The n.sup.-type drift region has an n-type impurity concentration is, for example, about 110.sup.14/cm.sup.3 to 110.sup.16/cm.sup.3. The n.sup.-type drift region has a boron concentration that is substantially lower than an n-type impurity concentration of the n.sup.-type drift region and that, for example, is about 110.sup.14/cm.sup.3 or less. During epitaxial growth of the n.sup.-type drift region, automatic doping of boron to the n.sup.-type drift region is suppressed, whereby the boron concentration of the n.sup.-type drift region is reduced and the n.sup.-type drift region in which no traps are present is formed.

A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states. A first region of the memory cell is in electrical contact with the floating body region. A second region of the memory cell is spaced apart from the first region and is also in electrical contact with the floating body region. A gate is positioned between the first and second regions. A back-bias region is configured to generate impact ionization when the memory cell is in one of the first and second states, and the back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of the first and second states.

A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states. A first region of the memory cell is in electrical contact with the floating body region. A second region of the memory cell is spaced apart from the first region and is also in electrical contact with the floating body region. A gate is positioned between the first and second regions. A back-bias region is configured to generate impact ionization when the memory cell is in one of the first and second states, and the back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of the first and second states.

A low voltage transient voltage suppressing (TVS) device supported on a semiconductor substrate supporting an epitaxial layer to form a bottom-source metal oxide semiconductor field effect transistor (BS-MOSFET) that comprises a trench gate surrounded by a drain region encompassed in a body region disposed near a top surface of the semiconductor substrate. The drain region interfaces with the body region constituting a junction diode. The drain region on top of the epitaxial layer constituting a bipolar transistor with a top electrode disposed on the top surface of the semiconductor functioning as a drain/collector terminal and a bottom electrode disposed on a bottom surface of the semiconductor substrate functioning as a source/emitter electrode. The body regions further comprises a surface body contact region electrically connected to a body-to-source short-connection thus connecting the body region to the bottom electrode functioning as the source/emitter terminal.

A low voltage transient voltage suppressing (TVS) device supported on a semiconductor substrate supporting an epitaxial layer to form a bottom-source metal oxide semiconductor field effect transistor (BS-MOSFET) that comprises a trench gate surrounded by a drain region encompassed in a body region disposed near a top surface of the semiconductor substrate. The drain region interfaces with the body region constituting a junction diode. The drain region on top of the epitaxial layer constituting a bipolar transistor with a top electrode disposed on the top surface of the semiconductor functioning as a drain/collector terminal and a bottom electrode disposed on a bottom surface of the semiconductor substrate functioning as a source/emitter electrode. The body regions further comprises a surface body contact region electrically connected to a body-to-source short-connection thus connecting the body region to the bottom electrode functioning as the source/emitter terminal.

A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states. A first region of the memory cell is in electrical contact with the floating body region. A second region of the memory cell is spaced apart from the first region and is also in electrical contact with the floating body region. A gate is positioned between the first and second regions. A back-bias region is configured to generate impact ionization when the memory cell is in one of the first and second states, and the back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of the first and second states.

A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states. A first region of the memory cell is in electrical contact with the floating body region. A second region of the memory cell is spaced apart from the first region and is also in electrical contact with the floating body region. A gate is positioned between the first and second regions. A back-bias region is configured to generate impact ionization when the memory cell is in one of the first and second states, and the back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of the first and second states.

Semiconductor memory cells, array and methods of operating are disclosed. In one instance, a memory cell includes a bi-stable floating body transistor and an access device; wherein the bi-stable floating body transistor and the access device are electrically connected in series.

Semiconductor memory cells, array and methods of operating are disclosed. In one instance, a memory cell includes a bi-stable floating body transistor and an access device; wherein the bi-stable floating body transistor and the access device are electrically connected in series.