A method for making a layered perovskite structure comprises: a) performing a vapor assisted surface treatment (VAST) of a substrate with a surface passivating agent; b) applying a layer of PbI.sub.2 to the passivating agent; c) exposing the PbI.sub.2 to methylammonium iodide (CH.sub.3NH.sub.3I) in an orthogonal solvent; and d) annealing the structure. A PEDOT:PSS coated ITO glass substrate may be used. The surface passivation agent may be one a chalcogenide-containing species with the general chemical formula (E.sub.3E.sub.4)N(E.sub.1E.sub.2)N′C═X where any one of E.sub.1, E.sub.2, E.sub.3 and E.sub.4 is independently selected from C1-C15 organic substituents comprising from 0 to 15 heteroatoms or hydrogen, and X is S, Se or Te, thiourea, thioacetamide, selenoacetamide, selenourea, H.sub.2S, H.sub.2Se, H.sub.2Te or LXH wherein L is a C.sub.n organic substituent comprising heteroatoms and X═S, Se, or Te. The passivating agent may be applied by spin-coating, inkjet-printing, slot-die-coating, aerosol-jet printing, PVD, CVD, and electrochemical deposition.

An ultraviolet (UV) photo-detecting device, including: a substrate; a first nitride layer disposed on the substrate; a second nitride layer disposed between the first nitride layer and the substrate; a light absorption layer disposed on the first nitride layer; and a Schottky junction layer disposed on the light absorption layer.

Integrated circuits described herein implement an x-input logic gate. The integrated circuit includes a plurality of Schottky diodes that includes x Schottky diodes and a plurality of source-follower transistors that includes x source-follower transistors. Each respective source-follower transistor of the plurality of source-follower transistors includes a respective gate node that is coupled to a respective Schottky diode. A first source-follower transistor of the plurality of source-follower transistors is connected serially to a second source-follower transistor of the plurality of source-follower transistors.

The present device is a thermophotovoltaic (TPV) cell adapted to charge the battery of an electronic device efficiently and cost-effectively. This is accomplished by specifically layering N-Type and P-type semiconductors in several layers while also introducing extrinsic doping agents that add to the conductivity of the oxides used for generating energy using ambient thermal energy. As such, electrical energy can effectively be drawn from a single heat reservoir.

The present device is a thermophotovoltaic (TPV) cell adapted to charge the battery of an electronic device efficiently and cost-effectively. This is accomplished by specifically layering N-Type and P-type semiconductors in several layers while also introducing extrinsic doping agents that add to the conductivity of the oxides used for generating energy using ambient thermal energy. As such, electrical energy can effectively be drawn from a single heat reservoir.

Embodiments of the invention provide a method of forming a group III-V material utilized in thin film transistor devices. In one embodiment, a gallium arsenide based (GaAs) layer with or without dopants formed from a solution based precursor may be utilized in thin film transistor devices. The gallium arsenide based (GaAs) layer formed from the solution based precursor may be incorporated in thin film transistor devices to improve device performance and device speed. In one embodiment, a thin film transistor structure includes a gate insulator layer disposed on a substrate, a GaAs based layer disposed over the gate insulator layer, and a source-drain metal electrode layer disposed adjacent to the GaAs based layer.

Embodiments of the invention provide a method of forming a group III-V material utilized in thin film transistor devices. In one embodiment, a gallium arsenide based (GaAs) layer with or without dopants formed from a solution based precursor may be utilized in thin film transistor devices. The gallium arsenide based (GaAs) layer formed from the solution based precursor may be incorporated in thin film transistor devices to improve device performance and device speed. In one embodiment, a thin film transistor structure includes a gate insulator layer disposed on a substrate, a GaAs based layer disposed over the gate insulator layer, and a source-drain metal electrode layer disposed adjacent to the GaAs based layer.

A fin structure for a semiconductor device, such as a FinFET structure, has first and second semiconductor layers and an air gap between the layers. The air gap may prevent current leakage. A FinFET device may be manufactured by first recessing and then epitaxially re-growing a source/drain fin, with the regrowth starting over a tubular air gap.

A photoelectric conversion element includes a PN junction formed from an N-type oxide layer and a P-type oxide layer. The P-type oxide layer is formed from an oxide having a perovskite structure.

A photoelectric conversion element includes a PN junction formed from an N-type oxide layer and a P-type oxide layer. The P-type oxide layer is formed from an oxide having a perovskite structure.