A multijunction solar cell including interconnected first and second discrete semiconductor regions disposed adjacent and parallel to each other including first top solar subcell, second (and possibly third) lattice matched middle solar subcells; a graded interlayer adjacent to the last middle solar subcell; and a bottom solar subcell adjacent to said graded interlayer being lattice mismatched with respect to the last middle solar subcell; wherein an opening is provided from the bottom side of the semiconductor substrate to one or more of the solar subcells so as to allow a discrete electrical connector to be made extending in free space and to electrically connect contact pads on one or more of the solar subcells.

The present disclosure provides a method of manufacturing a semiconductor device. Furthermore the present disclosure provides a photovoltaic device and a light emitting diode manufactured in accordance with the method. The method comprises the steps of forming a germanium layer using deposition techniques compatible with high-volume, low-cost manufacturing, such as magnetron sputtering, and exposing the germanium layer to laser light to reduce the amount of defects in the germanium layer. After the method is performed the germanium layer can be used as a virtual germanium substrate for the growth of III-V materials.

The invention discloses a laminated cell structure, the laminated cell structure comprising a top cell unit, a bottom cell unit, and an intermediate layer located between the top cell unit and the bottom cell unit; the intermediate layer being configured as a tunnel junction composed of a p.sup.+/n.sup.+ double-layer silicon thin film; the top cell unit comprising an electron transport layer, a perovskite photosensitive layer, a hole transport layer sequentially laminated in the direction from the distance to the vicinity with respect to the intermediate layer, and a front electrode provided on the electron transport layer; and the bottom cell unit being a PERC solar cell. The invention also correspondingly discloses a preparation method for the laminated cell structure. According to the invention, good perovskite cell performance can be obtained by adopting a silicon thin film tunnel junction structure. The laminated cell with the structure has high photoelectric conversion efficiency.

The invention discloses a laminated cell structure, the laminated cell structure comprising a top cell unit, a bottom cell unit, and an intermediate layer located between the top cell unit and the bottom cell unit; the intermediate layer being configured as a tunnel junction composed of a p.sup.+/n.sup.+ double-layer silicon thin film; the top cell unit comprising an electron transport layer, a perovskite photosensitive layer, a hole transport layer sequentially laminated in the direction from the distance to the vicinity with respect to the intermediate layer, and a front electrode provided on the electron transport layer; and the bottom cell unit being a PERC solar cell. The invention also correspondingly discloses a preparation method for the laminated cell structure. According to the invention, good perovskite cell performance can be obtained by adopting a silicon thin film tunnel junction structure. The laminated cell with the structure has high photoelectric conversion efficiency.

This invention describes a field-effect transistor in which the channel is formed in an array of quantum dots. In one embodiment the quantum dots are cladded with a thin layer serving as an energy barrier. The quantum dot channel (QDC) may consist of one or more layers of cladded dots. These dots are realized on a single or polycrystalline substrate. When QDC FETs are realized on polycrystalline or nanocrystalline thin films they may yield higher mobility than in conventional nano- or microcrystalline thin films. These FETs can be used as thin film transistors (TFTs) in a variety of applications. In another embodiment QDC-FETs are combined with: (a) coupled quantum well SWS channels, (b) quantum dot gate 3-state like FETs, and (c) quantum dot gate nonvolatile memories.

This invention describes a field-effect transistor in which the channel is formed in an array of quantum dots. In one embodiment the quantum dots are cladded with a thin layer serving as an energy barrier. The quantum dot channel (QDC) may consist of one or more layers of cladded dots. These dots are realized on a single or polycrystalline substrate. When QDC FETs are realized on polycrystalline or nanocrystalline thin films they may yield higher mobility than in conventional nano- or microcrystalline thin films. These FETs can be used as thin film transistors (TFTs) in a variety of applications. In another embodiment QDC-FETs are combined with: (a) coupled quantum well SWS channels, (b) quantum dot gate 3-state like FETs, and (c) quantum dot gate nonvolatile memories.

Provided is a power generation battery capable of improving power generation efficiency. The power generation battery includes a first layer, a second layer, and a filter layer. The first layer includes a semiconductor element that has a main absorption region in a visible light region and absorbs a light to generate electric power. The second layer, disposed on a side opposite to an incident direction side of the first layer, includes a semiconductor element that has a main absorption region in an infrared light region and absorbs light to generate electric power. The filter layer is disposed between the first layer and the second layer and blocks or absorbs a light in the visible light region.

A multijunction solar cell assembly and its method of manufacture including interconnected first and second discrete semiconductor body subassemblies disposed adjacent and parallel to each other, each semiconductor body subassembly including first top subcell, second (and possibly third) lattice matched middle subcells; a graded interlayer adjacent to the last middle solar subcell; and a bottom solar subcell adjacent to said graded interlayer being lattice mismatched with respect to the last middle solar subcell; wherein the interconnected subassemblies form at least a four junction solar cell by a series connection being formed between the bottom solar subcell in the first semiconductor body and the bottom solar subcell in the second semiconductor body.

A solar cell of an embodiment has a first solar cell, a second solar cell, and an intermediate layer between the first and second solar cells. The first solar cell has a Si layer as a light absorbing layer. The second solar cell has as a light absorbing layer one of a group I-III-VI.sub.2 compound layer and a group I.sub.2-II-IV-VI.sub.4 compound layer. The intermediate layer has an n.sup.+-type Si sublayer and at least one selected from a p.sup.+-type Si sublayer, a metal compound sublayer, and a graphene sublayer. The metal compound sublayer is represented by MX where M denotes at least one type of element selected from Nb, Mo, Pd, Ta, W, and Pt and X denotes at least one type of element selected from S, Se, and Te.

A solar cell of an embodiment has a first solar cell, a second solar cell, and an intermediate layer between the first and second solar cells. The first solar cell has a Si layer as a light absorbing layer. The second solar cell has as a light absorbing layer one of a group I-III-VI.sub.2 compound layer and a group I.sub.2-II-IV-VI.sub.4 compound layer. The intermediate layer has an n.sup.+-type Si sublayer and at least one selected from a p.sup.+-type Si sublayer, a metal compound sublayer, and a graphene sublayer. The metal compound sublayer is represented by MX where M denotes at least one type of element selected from Nb, Mo, Pd, Ta, W, and Pt and X denotes at least one type of element selected from S, Se, and Te.