A flip chip bonding method includes obtaining a die including a first substrate and an adhesive layer on the first substrate; bonding the die to a second substrate different from the first substrate; and curing the adhesive layer. The curing the adhesive layer includes heating the second substrate to melt the adhesive layer, and providing the adhesive layer and the second substrate with air having pressure greater than atmospheric pressure.

A chip mounting system (1) includes: a chip supplying unit (11) for supplying a chip (CP); a stage (31) for holding a substrate (WT) in an orientation in which a mounting face (WTf) for mounting the chip (CP) faces vertically downward (Z direction); a head (33H) for holding the chip (CP) from the vertically downward direction (Z direction); and a head drive unit (36) for, by causing vertically upward (+Z direction) movement of the head (33H) holding the chip (CP), causes the head (33H) to approach the stage (31) to mount the chip (CP) on the mounting face (WTf) of the substrate (WT).

A solder reflow apparatus includes a vapor generating chamber configured to accommodate a heat transfer fluid and to accommodate saturated vapor generated by heating the heat transfer fluid; a heater configured to heat the heat transfer fluid accommodated in the vapor generating chamber; a substrate stage configured to be movable upward and downward within the vapor generating chamber, the substrate stage including a seating surface; vapor passages penetrating the substrate stage and configured to allow the vapor to move therethrough; and suction passages penetrating the substrate stage to be open to the seating surface and in which at least a partial vacuum is generated.

A soldering device includes a control unit to predict a final rise temperature of an electronic device, based on power of a light pulse from at least one pulsed light irradiator, a weight of the electronic device, a real-time temperature of the electronic device, the quantity of exposures of the light pulse, and an irradiation period of the light pulse, and change a condition of the light pulse, based on a predicted result. A soldering method includes calculating power of the light pulse based on a time width of the light pulse, measuring a temperature of the electronic device, and predicting a final rise temperature of the electronic device, based on the calculated power, a weight of the electronic device, the measured temperature, the quantity of exposures of the light pulse, and the irradiation period.

A reliability cover that is disposed over at least one of an integrated circuit package and a Si die of the integrated circuit package is disclosed. The integrated circuit package is mountable to a printed circuit board via a plurality of solder balls. The reliability cover is configured to reduce a difference in a coefficient of thermal expansion between the integrated circuit package and the printed circuit board, and between the Si die and a substrate of the integrated circuit package by a threshold value.

A method includes picking up a first package component, removing an oxide layer on an electrical connector of the first package component, placing the first package component on a second package component after the oxide layer is removed, and bonding the first package component to the second package component.

A semiconductor manufacturing method of mounting a semiconductor chip or a stacked body of semiconductor chips on a support substrate placed on a stage, determines whether a predetermined condition is satisfied during a mounting processing of the semiconductor chip or the stacked body, evacuates, together with the support substrate, the semiconductor chip or the stacked body that has mounted on the support substrate before the determination when it is determined that the predetermined condition is satisfied, determines whether to resume the mounting processing of the semiconductor chip or the stacked body after the evacuation; and returns the evacuated semiconductor chip or the evacuated stacked body to a position before the evacuation and continuing the mounting processing when it is determined that the mounting processing is resumed.

A stacked device including a first substrate that includes a quantum information processing device, a second substrate bonded to the first substrate, and multiple bump bonds and at least one pillar between the first substrate and the second substrate. Each bump bond of the multiple bump bonds provides an electrical connection between the first substrate and the second substrate. At least one pillar defines a separation distance between a first surface of the first substrate and a first surface of the second substrate. A cross-sectional area of each pillar is greater than a cross-sectional area of each bump bond of the multiple bump bonds, where the cross-sectional area of each pillar and of each bump bond is defined along a plane parallel to the first surface of the first substrate or to the first surface of the second substrate.

A method for digital direct recording of an artwork representing electric connections of components on a substrate includes receiving data representing the artwork, analyzing the artwork representation to identify sections that are similar and sections that are unique and to identify locations of the components in the artwork, and dividing the artwork into modules corresponding to the identified sections, providing a set of unique modules and a set of redundant modules. The method also includes rasterizing each unique module to provide rasterized modules, dividing the rasterized modules into submodules, and receiving measurements representing positions of the components on the substrate. The method also includes receiving measurements representing the position of the substrate, calculating the differences between the measured positions of the components and the artwork positions of the components, calculating modifications for each of the sub modules to compensate for the differences, and recording the modified submodules onto the substrate to form a modified artwork on the substrate.

A chip-placing method for performing an image alignment of chip placement comprises a chip pick-up step, a reference-image capturing step, an alignment-image capturing step, a calculating and processing step, a calibration adjusting step and a placing step. An image(s) of a marking member and a chip sucked by a chip-placing member is/are captured from an opposite direction so as to obtain a relative position information of the chip in relation to the marking member. An image showing the marking member and the substrate is captured from a backside so as to obtain a relative position information of the marking member in relation to the substrate. A position calibration relationship information of the position of the chip in relation to a to-be-placed location of the substrate is obtained according to those relative position information. Therefore, a relative position of the chip-placing member in relation to the to-be-placed location is calibrated.