A semiconductor device includes: a semiconductor element; an element conductor having an element mounting surface on which the semiconductor element is mounted; a connection conductor that is arranged apart from the element conductor and has a connection surface on an upper part thereof; a connecting line connecting the semiconductor element and the connection surface of the connection conductor; and an encapsulation resin that encapsulates the semiconductor element, the element conductor, the connection conductor, and the connecting line, wherein: a parasitic capacitance reducing structure is provided in at least one of facing side surfaces of the element conductor and of the connection conductor, the facing side surfaces being arranged to face each other.

A semiconductor device includes: a semiconductor element; an element conductor having an element mounting surface on which the semiconductor element is mounted; a connection conductor that is arranged apart from the element conductor and has a connection surface on an upper part thereof; a connecting line connecting the semiconductor element and the connection surface of the connection conductor; and an encapsulation resin that encapsulates the semiconductor element, the element conductor, the connection conductor, and the connecting line, wherein: a parasitic capacitance reducing structure is provided in at least one of facing side surfaces of the element conductor and of the connection conductor, the facing side surfaces being arranged to face each other.

A light emitting element, a light emitting device and a manufacturing method thereof are provided. The manufacturing method of the light emitting device includes forming a first electrode and a second electrode spaced apart from each other on a substrate on which the light emitting area is defined; injecting a solution including a light emitting element and a liquid crystal molecule into the light emitting area; and aligning the light emitting element such that the first electrode and the second electrode are electrically coupled; wherein the light emitting element includes a first semiconductor layer; a second semiconductor layer; an active layer interposed between the first semiconductor layer and the second semiconductor layer; an insulation layer formed to surround an outer surface of the active layer; and an organic ligand layer formed on an outer surface of the insulating layer.

A method for transferring a micro device is provided. The method includes: preparing a carrier substrate with the micro device thereon, wherein an adhesive layer is between and in contact with the carrier substrate and the micro device; picking up the micro-device from the carrier substrate by a transfer head; forming a liquid layer on a receiving substrate; and placing the micro device over the receiving substrate by the transfer head such that the micro device is in contact with the liquid layer and is gripped by a capillary force; and moving the transfer head away from the receiving substrate such that the micro device is detached from the transfer head and is stuck to the receiving substrate.

A method for transferring a micro device is provided. The method includes: preparing a carrier substrate with the micro device thereon, wherein an adhesive layer is between and in contact with the carrier substrate and the micro device; picking up the micro-device from the carrier substrate by a transfer head; forming a liquid layer on a receiving substrate; and placing the micro device over the receiving substrate by the transfer head such that the micro device is in contact with the liquid layer and is gripped by a capillary force; and moving the transfer head away from the receiving substrate such that the micro device is detached from the transfer head and is stuck to the receiving substrate.

Disclosed herein is a method of forming an electrical connecting structure having nano-twins copper. The method includes the steps of (i) forming a first nano-twins copper layer including a plurality of nano-twins copper grains; (ii) forming a second nano-twins copper layer including a plurality of nano-twins copper grains; and (iii) joining a surface of the first nano-twins copper layer with a surface of the second nano-twins copper layer, such that at least a portion of the first nano-twins copper grains grow into the second nano-twins copper layer, or at least a portion of the second nano-twins copper grains grow into the first nano-twins copper layer. An electrical connecting structure having nano-twins copper is provided as well.

Disclosed herein is a method of forming an electrical connecting structure having nano-twins copper. The method includes the steps of (i) forming a first nano-twins copper layer including a plurality of nano-twins copper grains; (ii) forming a second nano-twins copper layer including a plurality of nano-twins copper grains; and (iii) joining a surface of the first nano-twins copper layer with a surface of the second nano-twins copper layer, such that at least a portion of the first nano-twins copper grains grow into the second nano-twins copper layer, or at least a portion of the second nano-twins copper grains grow into the first nano-twins copper layer. An electrical connecting structure having nano-twins copper is provided as well.

A packaged assembly is disclosed, including thermal interface material dispensed on an organic package and methods of manufacturing. The method includes dispensing a thermal interface material (TIM) on an electronic assembly. The method further includes removing volatile species of the TIM, prior to lid placement on the electronic assembly. The method further includes placing the lid on the TIM, over the electronic assembly. The method further includes pressing the lid onto the electronic assembly.

An integrated circuit packaging method, including: a top surface of a substrate, a bottom surface of the substrate, or the interior of the substrate is provided with circuit layers, and the circuit layers are provided with circuit pins; a component element is mounted on the substrate, and a surface of the component element facing the substrate is provided with component pins; connection through holes are formed on the substrate, the connection through holes are made to abut on the circuit pins, and a first opening of the connection through holes is abutted on the component pins; conductive layers are fabricated inside of the connection through holes by means of a second opening of the connection through holes, and the conductive layers electrically connect the component pins with the circuit pins.

A mounting apparatus of a chip including a mechanism configured to arrange a front surface of a chip and a front surface of a substrate to face each other such that a back surface of the chip is attached to a sheet, the sheet having a first portion corresponding to the selected chip and a the second portion arranged at a periphery of the first portion corresponding to the selected chip in the sheet when seen in a direction perpendicular to the front surface of the substrate; a holding mechanism moving in a direction that is not perpendicular to the front surface of the substrate and arranged to hold the second portion of the sheet; and a pushing mechanism for pushing the back surface of the chip through the first portion of the sheet so that the front surface of the chip is brought close to the front surface of the substrate with the first portion deformed in a state where the second portion is held by the holding mechanism, and configured to release the pushing mechanism from the first portion of the sheet to strip the sheet from the back surface of the chip.