The present invention relates to a method and apparatus for manufacturing a plurality of electronic circuits, each electronic circuit comprising a respective flexible first portion, comprising a respective group of contact pads (contacts), and a respective flexible integrated circuit, IC, comprising a respective group of terminals and mounted on the respective group of contact pads with each terminal in electrical contact with a respective contact pad, the method comprising:

providing (e.g. manufacturing) a flexible first structure comprising the plurality of first portions;

providing (e.g. manufacturing) a second structure comprising the plurality of flexible ICs and a common support arranged to support the plurality of flexible ICs;

dispensing an adhesive onto the first structure and/or onto the flexible ICs;

transferring said flexible ICs from the common support onto the flexible first structure such that each group of terminals is mounted on (brought into electrical contact with) a respective group of contact pads to form an electronic circuit,

providing a heated surface and an opposing surface together having a gap therebetween,

transferring the flexible first structure, comprising the electronic circuits, between the heated surface and the opposing surface such that the adhesive is cured by application of heat and pressure from the heated surface and the opposing surface thereby adhering the IC onto the respective first portion.

The present invention relates to a method and apparatus for manufacturing a plurality of electronic circuits, each electronic circuit comprising a respective flexible first portion, comprising a respective group of contact pads (contacts), and a respective flexible integrated circuit, IC, comprising a respective group of terminals and mounted on the respective group of contact pads with each terminal in electrical contact with a respective contact pad, the method comprising:

providing (e.g. manufacturing) a flexible first structure comprising the plurality of first portions;

providing (e.g. manufacturing) a second structure comprising the plurality of flexible ICs and a common support arranged to support the plurality of flexible ICs;

dispensing an adhesive onto the first structure and/or onto the flexible ICs;

transferring said flexible ICs from the common support onto the flexible first structure such that each group of terminals is mounted on (brought into electrical contact with) a respective group of contact pads to form an electronic circuit,

providing a heated surface and an opposing surface together having a gap therebetween,

transferring the flexible first structure, comprising the electronic circuits, between the heated surface and the opposing surface such that the adhesive is cured by application of heat and pressure from the heated surface and the opposing surface thereby adhering the IC onto the respective first portion.

A method of manufacturing a multi-layer wafer is provided. The method comprises creating under bump metallization (UMB) pads on each of the two heterogeneous wafers; applying a conductive means above the UMB pads on at least one of the two heterogeneous wafers; and low temperature bonding the two heterogeneous wafers to adhere the UMB pads together via the conductive means. At least one stress compensating polymer layer may be applied to at least one of two heterogeneous wafers. The multi-layer wafer comprises two heterogeneous wafers, each of the heterogeneous wafer having UMB pads and at least one of the heterogeneous wafers having a stress compensating polymer layer and a conductive means applied above the UMB pads on at least one of the two heterogeneous wafers. The two heterogeneous wafers low temperature bonded together to adhere the UMB pads together via the conductive means.

A method of manufacturing a multi-layer wafer is provided. The method comprises creating under bump metallization (UMB) pads on each of the two heterogeneous wafers; applying a conductive means above the UMB pads on at least one of the two heterogeneous wafers; and low temperature bonding the two heterogeneous wafers to adhere the UMB pads together via the conductive means. At least one stress compensating polymer layer may be applied to at least one of two heterogeneous wafers. The multi-layer wafer comprises two heterogeneous wafers, each of the heterogeneous wafer having UMB pads and at least one of the heterogeneous wafers having a stress compensating polymer layer and a conductive means applied above the UMB pads on at least one of the two heterogeneous wafers. The two heterogeneous wafers low temperature bonded together to adhere the UMB pads together via the conductive means.

A multi-layer wafer and method of manufacturing such wafer are provided. The method includes creating under bump metallization (UMB) pads on each of the two heterogeneous wafers; applying a conductive means above the UMB pads on at least one of the two heterogeneous wafers; and low temperature bonding the two heterogeneous wafers to adhere the UMB pads together via the conductive means. At least one stress compensating polymer layer may be applied to at least one of two heterogeneous wafers. The multi-layer wafer comprises two heterogeneous wafers, each of the heterogeneous wafer having UMB pads and at least one of the heterogeneous wafers having a stress compensating polymer layer and a conductive means applied above the UMB pads on at least one of the two heterogeneous wafers. The two heterogeneous wafers low temperature bonded together to adhere the UMB pads together via the conductive means.

A multi-layer wafer and method of manufacturing such wafer are provided. The method includes creating under bump metallization (UMB) pads on each of the two heterogeneous wafers; applying a conductive means above the UMB pads on at least one of the two heterogeneous wafers; and low temperature bonding the two heterogeneous wafers to adhere the UMB pads together via the conductive means. At least one stress compensating polymer layer may be applied to at least one of two heterogeneous wafers. The multi-layer wafer comprises two heterogeneous wafers, each of the heterogeneous wafer having UMB pads and at least one of the heterogeneous wafers having a stress compensating polymer layer and a conductive means applied above the UMB pads on at least one of the two heterogeneous wafers. The two heterogeneous wafers low temperature bonded together to adhere the UMB pads together via the conductive means.

A magnetic polymer for use in microelectronic fabrication includes a polymer matrix and a plurality of ferromagnetic particles disposed in the polymer matrix. The magnetic polymer can be part of an insulation layer in an inductor formed in one or more backend wiring layers of an integrated device. The magnetic polymer can also be in the form of a magnetic epoxy layer for mounting contacts of the integrated device to a package substrate.

A stacked semiconductor device is provided, including a first semiconductor structure, a second semiconductor structure and a bonding structure disposed between the first and second semiconductor structures. The first semiconductor structure and the second semiconductor structure include first conductive pillars and second conductive pillars, respectively. The first semiconductor structure is stacked above the second semiconductor structure. The bonding structure contacts the first conductive pillars and the second conductive pillars, wherein the bonding structure comprises conductive paths for electrically connecting the first conductive pillars and the second conductive pillars.

A semiconductor device includes a conductive member, a solder layer, a chip, a coating film, an insulating part, and a sealing resin. The solder layer is located on the conductive member. The chip is located on the solder layer. The coating film is insulative. The coating film is located on the chip. The coating film includes a first covering part. The first covering part covers an outer perimeter edge of an upper surface of the chip. The insulating part is located on the coating film. The sealing resin seals the solder layer, the chip, the coating film, and the insulating part.

A magnetic polymer for use in microelectronic fabrication includes a polymer matrix and a plurality of ferromagnetic particles disposed in the polymer matrix. The magnetic polymer can be part of an insulation layer in an inductor formed in one or more backend wiring layers of an integrated device. The magnetic polymer can also be in the form of a magnetic epoxy layer for mounting contacts of the integrated device to a package substrate.