A circuit includes an amplifier to amplify an input signal and generate an output signal. The circuit also includes a tuning network to tune frequency response of the amplifier. The tuning network includes at least one tunable capacitor, which includes at least one micro-electro mechanical system (MEMS) capacitor. The amplifier could include a first die, the at least one MEMS capacitor could include a second die, and the first die and the second die could be integrated in a single package. The at least one MEMS capacitor could include a MEMS superstructure over a control structure, which is to control the MEMS superstructure and tune the capacitance of the at least one MEMS capacitor.

A multi-level, multi-branch outphasing amplifier (20-1) includes a first branch group circuit (22-1) including a first branch circuit (11) receiving a first RF input signal (S.sub.1(t)) and first control information (S.sub.11.sub._Ctrl=V.sub.DD) and a second branch circuit (12) receiving the first input signal and second control information (S.sub.12.sub._Ctrl). Each of the first (11) and second (12) branch circuits includes a power amplifier. The second control information enables the second branch circuit to be switched on or off while the first branch circuit (12) remains on. A second branch group circuit (22-2) includes a third branch circuit (21) receiving a second RF input signal (S.sub.2(t)) and third control information (S.sub.21.sub._Ctrl=V.sub.DD) and a fourth branch circuit (22) receiving the second input signal (S.sub.2(t)) and fourth control information (S.sub.22.sub._Ctrl). Each of the third and fourth branch circuits includes a power amplifier. The fourth control information enables the fourth branch circuit to be switched on or off while the third branch circuit remains on. A combiner (24) combines output signals of the power amplifiers to produce an output signal (S.sub.OUT(t)).

The circuit includes a transformer having a first primary coil coupled to a first power amplifier (PA), a second primary coil coupled to a second PA, and a secondary coil. The secondary coil supplies a current to an antenna based on a first direction of a first phase of a first amplified constant-envelope signal in the first primary coil with respect to a second phase of a second amplified constant-envelope signal in the second primary coil. A first load impedance is associated with the first PA and a second load impedance is associated with the second PA. The first load impedance and the second load impedance receive currents from the first PA and second PA, respectively, based on a second direction of the first phase of the first amplified constant-envelope signal with respect to the second phase of the second amplified constant-envelope signal.

A driver circuit for a composite power amplifier configured to operate in at least one Chireix-mode a first and a second sub-amplifier for amplification of an input signal into an output signal is disclosed. An input network of the driver circuit comprises a means configured to provide a first signal which is linearly derivable from the input signal, and a second signal which is non-linearly derivable from the input signal. The input network combines the first signal, at zero degrees phase shift, and the second signal, at 90 degrees phase shift, to obtain a first feeding signal for the first sub-amplifier. Furthermore, the input network combines the first signal, at 180 degrees phase shift, and the second signal, at 90 degrees phase shift, to obtain a second feeding signal for the second sub-amplifier.

Aspects of the disclosure relate to a radio frequency phase shifter. An example includes an amplification stage to produce an amplified voltage, the amplification stage having a first amplifier with a first input coupled to a first output of a hybrid coupler and a second amplifier with a complementary second input coupled to a complementary second output of the hybrid coupler. A vector modulation stage coupled to the amplification stage receives the amplified voltage and produces a modulated vector, the vector modulation stage has an in-phase section and a quadrature section to control the phase of the modulated vector in response to a phase control signal. A varactor coupled across the first input and the second input of the amplification stage adjusts the capacitance between the first input and the second input in response to a capacitance control signal.

An outphasing amplifier includes a first amplifier, a second amplifier, and a combiner. The combiner includes a first node inputting a first signal, a second node inputting a second signal, a third node outputting a combined signal as an output signal, a first impedance converter connected to the first node and the third node, a second impedance converter connected to the second node and the third node, a first open stub wherein when an electrical length converted into a phase at a center frequency of an operating frequency band is ?3, and an outphasing angle when a power of the output signal has a minimum value is ?bo, ?3 is different from 180???bo and +?bo, and a second open stub wherein when an electrical length converted into a phase at the center frequency is ?4, ?4 is different from 180???bo and +?bo.

An encoding modulation method and transmitter are described. The method includes: oversampling and noise-shaping received multi-bit data to obtain N bits of data; using the N bits of data as a lookup table address to obtain a PWM puke modulation signal; multiplexing synthetic orthogonal (IQ) complex data of the PWM pulse modulation signal to be real number signal data; and converting the multiplexed real number signal data to an analog signal for power amplification and output, N being an integer representing a smaller number of bits than the received multi-bit data.

A multi-standard transmitter architecture with digitally upconverted intermediate frequency (IF) outphased signals is disclosed. The transmitter architecture includes a Gallium Nitride (GaN) power amplifier (PA) circuit having a Current Mode Class-D (CMCD) configuration. The GaN PA circuit includes a lower switching device electrically coupled to an input to receive an input RF signal and an upper switching device to switchably electrically couple the first switching device to a power supply to drive an antenna circuit based on the input RF signal. Thus, a reconfigurable transmitter architecture is disclosed that utilizes a high-speed Gallium Nitride (GaN) driver to achieve a peak drain efficiency of at least 85% while delivering output power of 10 W at 1 GHz frequency, for example.

An outphasing power management circuit for radio frequency (RF) beamforming is disclosed. The outphasing power management circuit includes a first outphasing amplifier branch consisting of a plurality of first power amplifiers and a second outphasing amplifier branch consisting of a plurality of second power amplifiers. A controller operates the first outphasing amplifier branch and the second outphasing amplifier branch as a pair of outphasing power amplifiers. The first outphasing amplifier branch generates a plurality of first output signals, and the second outphasing amplifier branch generates a plurality of second output signals. The first output signals and the second output signals are transmitted in an RF beam without being combined. As such, it is possible to support RF beamforming with a reduced number of power amplifiers and/or direct current (DC) to DC converters, thus helping to improve efficiency and reduce cost.

A circuit includes an amplifier configured to amplify an input signal and generate an output signal. The circuit also includes a tuning network configured to tune frequency response of the amplifier. The tuning network includes at least one tunable capacitor, where the at least one tunable capacitor includes at least one micro-electro mechanical system (MEMS) capacitor. The amplifier could include a first die, the at least one MEMS capacitor could include a second die, and the first die and the second die could be integrated in a single package. The at least one MEMS capacitor could include a MEMS superstructure disposed over a control structure, where the control structure is configured to control the MEMS superstructure and tune the capacitance of the at least one MEMS capacitor.