A receiver includes a gain adjusting circuit and a timing control circuit. The gain adjusting circuit adjusts the strength of an input signal according to a gain value to generate an adjusted input signal. The timing control circuit generates a control signal according to the input signal or the adjusted input signal to determine a time point at which the gain adjusting circuit changes the gain value.

A wireless device, method, and signal for use in communication of a wireless packet between transmitting device and a wireless receiving device via a plurality of antennas, wherein a signal generator generates wireless packet including a short-preamble sequence used for a first automatic gain control (AGC), a first long-preamble sequence, a signal field used for conveying a length of the wireless packet, an AGC preamble sequence used for a second AGC to be performed after the first AGC, a second long-preamble sequence, and a data field conveying data. The AGC preamble sequence is transmitted in parallel by the plurality of antennas.

A digitally controlled amplifier (DCA) has a drive (e.g., bipolar junction) transistor with a base to accept an input signal and a collector to supply an output signal. The DCA also includes n switchable gain amplifier networks (SGANs). Each SGAN has a signal input connected to the collector of the drive transistor, an input to accept a logic signal, and a signal output to supply a switchable gain AC output signal to a load in response to the logic signal. The SGAN signal outputs are connected together, typically in parallel, to supply a digitally controlled AC output gain. An auxiliary SGAN may be connected to supply a constant gain AC output signal. Each of the SGANs may have an identical switchable AC gain and accept an independent logic signal to supply (n+1) levels of digitally controlled AC output gain.

A system, in an active reflector device, adjusts a first amplification gain of each of a plurality of radio frequency (RF) signals received at a receiver front-end from a first equipment via a first radio path of an NLOS radio path. A first phase shift is performed on each of the plurality of RF signals with the adjusted first amplification gain. A combination of the plurality of first phase-shifted RF signals is split at a transmitter front-end. A second phase shift on each of the split first plurality of first phase-shifted RF signals is performed. A second amplification gain of each of the plurality of second phase-shifted RF signals is adjusted.

The embodiments of the disclosure introduce a novel receiver having a smart listening mode for reducing the current consumption of a receiver while waiting for a data packet. In the smart listening mode, the receiver temporarily disables one signal path of a quadrature signal (e.g., I or Q path) until the receiver detects an arrival of data packet via a second signal path of the quadrature signal. The receiver continuously monitors the enabled signal path for the incoming data packet via in-channel energy. After the incoming data packet is detected, it is further determined whether the incoming data packet is a valid data packet. If not, one of the signal paths would be disabled again. As a result, the current consumption of the receiver is reduced while waiting for an incoming data packet.

A receiver has a differential transimpedance amplifier (4) with two inputs and two outputs. The differential transimpedance amplifier (4) provides a differential output and this is peak-detected (15, 16) to provide amplitude reference signals. The differential transimpedance amplifier output and the amplitude reference signals are fed to a differential summing amplifier (10), which provides a fully differential signal to a comparator, or to an automatic gain control circuit (5) to regulate the differential transimpedance amplifier gain. The differential summing amplifier (10) output is a fully differential signal, thereby having lower distortion for DC and burst mode receiver applications.

According to one mode of the inventive concept, an amplification device includes a first amplifier configured to amplify an input multi-band signal to a first level, a separating unit configured to separate the multi-band signal having the first level into a first band signal and a second band signal, and a second amplifier configured to amplify the second band signal to a second level.

A system, in an active reflector device, adjusts a first amplification gain of each of a plurality of radio frequency (RF) signals received at a receiver front-end from a first equipment via a first radio path of an NLOS radio path. A first phase shift is performed on each of the plurality of RF signals with the adjusted first amplification gain. A combination of the plurality of first phase-shifted RF signals is split at a transmitter front-end. A second phase shift on each of the split first plurality of first phase-shifted RF signals is performed. A second amplification gain of each of the plurality of second phase-shifted RF signals is adjusted.

A gain controller sets a gain code indicating an optimum gain, a cutoff frequency code indicating a cutoff frequency, and a number of bits code indicating a number of bits. An AEQ/VGA gain controller sets a frequency characteristic code indicating a frequency characteristic, a gain code indicating a gain after correction, and a number of bits code indicating a number of bits. An AEQ/VGA amplifies a baseband received signal on the basis of a gain code and corrects a frequency characteristic of the baseband received signal on the basis of a frequency characteristic code. An HPF cuts off a band below a cutoff frequency of an output signal from the AEQ/VGA on the basis of a cutoff frequency code. An ADC quantizes an output signal from the HPF using a number of bits based on a number of bits code and generates a digital received signal.

An amplifying circuit includes a first gain adjusting circuit, a second gain adjusting circuit, a load circuit and a switch module. When the amplifying circuit operates in a first mode, the first gain adjusting circuit receives a first input signal, and generates a first output signal to a second output terminal of the amplifying circuit via the load circuit and the switch module; and when the amplifying circuit operates in a second mode, the second gain adjusting circuit receives a second input signal, and generates a second output signal to a first output terminal of the amplifying circuit via the load circuit and the switch module.