A driver for a power field-effect transistor includes a first and second circuits that apply respective charge currents to a gate of the power field-effect transistor when a control signal has a first logic value and the voltage between the gate and the source is smaller than a first threshold voltage and greater than a second threshold voltage. Third and fourth circuits apply respective discharge currents to the gate when the control signal has a second logic value and the voltage between the gate and the source is greater than a third threshold voltage and smaller than a fourth threshold voltage. The driver may include at least one field-effect transistor configured to generate at least one of the first, second, third or fourth threshold voltage.

An electronic circuit includes an input configured to receive an input signal and an output configured to be coupled to load, an output transistor including a load path and a control node, the load path being connected between the output and a first supply node, a drive transistor including a load path and a control node, the load path being connected to the control node of the output transistor, a first electronic switch connected in series with the load path of the drive transistor, a biasing circuit including an internal impedance and connected between the control node of the drive transistor and the first supply node, and a control circuit configured to receive the input signal and to drive the first electronic switch based on the input signal.

Integrated circuits (ICs) that avoid or mitigate creation of changes in accumulated charge in a silicon-on-insulator (SOI) substrate, particularly an SOI substrate having a trap rich layer. In one embodiment, a FET is configured such that, in a standby mode, the FET is turned OFF while maintaining essentially the same V.sub.DS as during an active mode. In another embodiment, a FET is configured such that, in a standby mode, current flow through the FET is interrupted while maintaining essentially the same V.sub.GS as during the active mode. In another embodiment, a FET is configured such that, in a standby mode, the FET is switched into a very low current state (a “trickle current” state) that keeps both V.sub.GS and V.sub.DS close to their respective active mode operational voltages. Optionally, S-contacts may be formed in an IC substrate to create protected areas that encompass FETs that are sensitive to accumulated charge effects.

A method of operating a driver circuit includes receiving a data signal at a first input of an amplification circuit; amplifying, using the amplification circuit, the data signal to produce an output signal through an output pin; attenuating, using a feedback network, the output signal to produce a feedback signal; coupling the feedback signal to a second input of the amplification circuit; detecting, using a control circuit, a fault condition; and decoupling, responsive to detecting the fault condition, the feedback signal from the second input of the amplification circuit. In some embodiments, the driver circuit transmits a fault condition signal to an electronic control unit of an automobile.

A technique is provided that reduces dullness of a potential provided to a line such as gate line on an active-matrix substrate to enable driving the line at high speed and, at the same time, reduces the size of the picture frame region. On an active-matrix substrate (20a) are provided gate lines (13G) and source lines. On the active-matrix substrate (20a) are further provided: gate drivers (11) each including a plurality of switching elements, at least one of which is located in a pixel region, for supplying a scan signal to a gate line (13G); and lines (15L1) each for supplying a control signal to the associated gate driver (11). A control signal is supplied by a display control circuit (4) located outside the display region to the gate drivers (11) via the lines (15L1). In response to a control signal supplied, each gate driver (11) drives the gate line (13G) to which it is connected.

An off chip driver circuit includes a first power rail, a second power rail, an input/output pad, a pull-up circuit, a pull-down circuit. The pull-up circuit is configured to selectively activate at least one of charging paths between the first power rail and the input/output pad. The pull-up circuit includes a first resistor and PMOS transistors arranged on the charging paths, and the first resistor is coupled between the first power rail and the PMOS transistors. The pull-down circuit is configured to selectively activate at least one of discharging paths between the second power rail and the input/output pad. The pull-down circuit includes a second resistor and NMOS transistors arranged on the discharging paths, and the second resistor is coupled between the second power rail and the NMOS transistors.

A gate driver circuit drives a switching transistor. A variable current source generates a reference current configured to switch between a first current amount and a second current amount smaller than the first current amount. A current distribution circuit is configured to switch between a source enabled state in which a source current proportional to the reference current is sourced to a gate node of the switching transistor and a disabled state in which the source current is made equal to zero. A first transistor fixes the gate node of the switching transistor to a high voltage in an on-state of the first transistor. A second transistor fixes the gate node of the switching transistor to a low voltage in an on-state of the second transistor.

A gate voltage magnitude compensation equalization method and circuit for series operation of power switch transistors are provided. A dynamic voltage equalization of series-connected power switch transistors is implemented by using sampling principles where voltages of the power switch transistors are controlled by gate voltage magnitude and unbalanced voltage differentials are converted into unbalanced current differentials of buffer currents. The gate voltage magnitude compensation equalization method and circuit relates to differential control and works in a dynamic voltage change process of the series-connected power switch transistors, without having a negative effect on operation of the power switch transistors under normal operating conditions. Only adopting passive devices, the gate voltage magnitude compensation equalization circuit has a simple structure, is easy to integrate on a device drive board, implements response tracking of unbalanced voltage and voltage equalization of the series-connected power switch transistors, and improve speedability and stability of voltage equalization control.

Devices having one primary transistor, or a plurality of primary transistors in parallel, protect electrical circuits from overcurrent conditions. Optionally, the devices have only two terminals and require no auxiliary power to operate. In those devices, the voltage drop across the device provides the electrical energy to power the device. A third or fourth terminal can appear in further devices, allowing additional overcurrent and overvoltage monitoring opportunities. Autocatalytic voltage conversion allows certain devices to rapidly limit or block nascent overcurrents.

A wiring of a semiconductor switch having a gate, a collector or a drain, and an emitter or a source, includes a first arrangement having a first capacitor connected in series with a parallel connection having a first resistor and a first diode. The first arrangement is connected between the gate and the collector or drain, wherein the first diode is connected away from the gate in a flow direction. A second arrangement is connected in parallel with the first arrangement and includes a second capacitor connected in series with a parallel connection having a second resistor and a second diode, wherein the second diode lies toward the gate in the flow direction.