A method for non-linearity correction includes receiving a first output signal from a data signal path containing a first analog-to-digital converter and receiving a second output signal from a second analog-to-digital converter. The method also includes generating first non-linearity coefficients using the first output signal and generating second non-linearity coefficients using the first and second output signals. The method further includes applying, by a non-linearity corrector in the data signal path, the first and second non-linearity coefficients to compensate for non-linearity components in a digitized signal output from the first analog-to-digital converter to generate a corrected digitized signal.

A distance measuring method and an electronic laser distance measuring module, in particular for use in a distance measuring apparatus, especially configured as a laser tracker, tachymeter, laser scanner, or profiler, for fast signal detection with an analog-to-digital converter, wherein conversion errors that arise in the context of a signal digitization, in particular timing, gain and offset errors of the ADC, are compensated for by means of variation of the sampling instants.

A dither capacitor, separate from the capacitor sampling the input signal, can be used to inject the additive dither in the switched-capacitor network of the track and hold circuit. This implementation can be referred to as a split-capacitor dither injection. The dither capacitor can be connected to a summing node of the switched-capacitor network. Using a separate capacitor allows the dither to be isolated from the capacitor that is sampling the input signal and avoids kick-back errors.

A method of calibrating capacitive array of a resistor-capacitor hybrid successive approximation register analog-to-digital converter (RC-hybrid SAR ADC) that includes a high M-bit capacitor DAC and a low N-bit resistor DAC. The method includes: disposing n unit capacitors in each capacitive array of the RC-hybrid SAR ADC, wherein n=2.sup.M1; sorting the capacitors in an ascending order according to their capacitances to form a sorted array, and selecting two capacitors C.sub.u(n/2)*, C.sub.u(n/2+1)* in the middle positions as a least significant bit (LSB) capacitor and a dummy capacitor, respectively; 4) obtaining a new array by forming each capacitor through adding two capacitors which have symmetrical positions with respect to the middle position(s) in the sorted array; and sorting the new array in an ascending order, and selecting the capacitor in the middle position as a higher bit capacitor. The method improves the static and dynamic performance of the SAR. ADC

An analog-to-digital converter (ADC) device includes ADC circuitries, a calibration circuitry, and a skew adjusting circuitry. The ADC circuitries convert an input signal according to interleaved clock signals, in order to generate first quantized outputs. The calibration circuitry performs at least one calibration operation according to the first quantized outputs to generate second quantized outputs. The skew adjusting circuitry analyzes time difference information within even-numbered sampling periods of the clock signals, in order to generate adjustment signals. The adjustment signals are for reducing a clock skew in the ADC circuitries.

Successive-approximation-register (SAR) analog-to-digital conversion technique continues to be one of the most popular analog-to-digital conversion techniques, due to their versatility, which allows providing high resolution output or high conversion rates. In addition, SAR analog-to-digital converters (ADC) have a modest circuit complexity that results in low-power dissipation. A SAR ADC is, typically, composed of a single comparator, a bank of capacitors and switches, in addition to, a control digital logic. However, the comparator input capacitance is input-signal dependent, and hence introduces non-linearity to the transfer characteristics of the ADC. A simple technique is devised to significantly reduce this non-linearity, by pre-distorting the sampled-and-held input signal using the same comparator input capacitance.

VCO ADCs consume relatively little power and require less area than other ADC architectures. However, when a VCO ADC is implemented by itself, the VCO ADC can have limited bandwidth and performance. To address these issues, the VCO ADC is implemented as a back end stage in a VCO-based continuous-time (CT) pipelined ADC, where the VCO-based CT pipelined ADC has a CT residue generation front end. Optionally, the VCO ADC back end has phase interpolation to improve its bandwidth. The pipelined architecture dramatically improves the performance of the VCO ADC back end, and the overall VCO-based CT pipelined ADC is simpler than a traditional continuous-time pipelined ADC.

An apparatus for calibrating an analog-to-digital converter is provided. The apparatus includes a reference input generation circuit configured to subsequently generate two reference inputs for calibrating the analog-to-digital converter. The two reference inputs both represent ramp waveforms, wherein the ramp waveforms represented by the two reference inputs are different from each other. Further, the apparatus includes a coupling circuit configured to controllably couple an input node of the analog-to-digital converter to either the reference input generation circuit or to a signal node capable of providing an analog input for digitization.

Digital to analog conversion generates an analog output corresponding to a digital input by controlling unit elements or cells using data bits of the digital input. The unit elements or cells individually make a contribution to the analog output. Due to process, voltage, and temperature variations, the unit elements or cells may have mismatches. The mismatches can degrade the quality of the analog output. To extract the mismatches, a transparent dither can be used. The mismatches can be extracted by observing the analog output, and performing a cross-correlation of the observed output with the dither. Once extracted, the unit elements or cells can be adjusted accordingly to reduce the mismatches.

Described are apparatus and methods for successive approximation register (SAR) analog to digital converter (ADC) (SAR ADC) with factoring and background clock calibration. An apparatus includes a SAR ADC configured to, in response to receiving an enable flag based on detection of an acquisition clock with a first logic state sent by a controller, sample and convert a pair of differential input signals using a sampling clock to obtain a defined number of samples in an acquisition clock cycle and a factoring circuit configured to obtain the defined number of samples from the SAR ADC using a capturing clock based on the sampling clock, factor the defined number of samples, and send a factored samples ready flag to the controller.