H03M13/616

Transmission method and reception device
11533066 · 2022-12-20 · ·

The present technology relates to a transmission method and a reception device for securing favorable communication quality in data transmission using an LDPC code. In group-wise interleaving, the LDPC code with a code length N of 17280 bits is interleaved in units of 360-bit bit groups 0 to 47. In group-wise deinterleaving, a sequence of the LDPC code after group-wise interleaving is returned to an original sequence. The present technology can be applied, for example, in a case of performing data transmission using an LDPC code, and the like.

Hardware architecture for local erasure correction in SSD/UFS via maximally recoverable codes

A hardware architecture for systematic erasure encoding includes first matrix constructor circuit that receives parity-check matrix H for codeword C, and the erased part of codeword C, and outputs matrix H.sub.1 of columns of H located on erased coordinates of code C; second matrix constructor circuit that receives matrix H and the erased part of codeword C and outputs matrix H.sub.2 of columns of H located on non-erased coordinates of code C; a neural network that calculates matrix J.sub.1 that is an approximate inverse of matrix H.sub.1. The matrix J.sub.1 is used to determine new erasures in the parity matrix H and new erased coordinates. Matrices H.sub.1 and H.sub.2 are updated, and the updated H.sub.1 is provided as feedback to the first matrix constructor circuit. A calculator circuit restores the erased coordinates of codeword C, from the matrix J.sub.1, matrix H.sub.2, and a non-erased part of codeword C.

APPARATUS AND METHOD FOR STABILIZING POWER IN A SEMICONDUCTOR DEVICE
20220390971 · 2022-12-08 ·

A power generation device includes a band gap reference (BGR) circuit configured to generate a reference voltage independent of an environmental change, and a voltage generation circuit configured to transfer an input power voltage based on a sum of the reference voltage and an internal ground voltage to generate an internal power voltage.

DECODING SYSTEMS AND METHODS FOR LOCAL REINFORCEMENT
20220393703 · 2022-12-08 ·

Embodiments of the present disclosure provide a scheme for decoding over a small subgraph which highly likely includes some errors. A controller is configured to: control the first decoder to decode the data, read from the memory device, using a parity check matrix for the error correction code; extract one or more subgraphs from the entire bipartite graph of the parity check matrix, which is defined by a plurality of variable nodes and a plurality of check nodes when a particular condition satisfied; and control the second decoder to decode the decoding result of the first decoder using a submatrix of the parity check matrix corresponding to the extracted subgraphs.

Transmitter and shortening method thereof

A transmitter is provided. The transmitter includes: an outer encoder configured to encode input bits to generate outer-encoded bits including the input bits and parity bits; a zero padder configured to generate a plurality of bit groups each of which is formed of a same number of bits, maps the outer-encoded bits to some of the bits in the bit groups, and pads zero bits to remaining bits in the bit groups, based on a predetermined shortening pattern, thereby to constitute Low Density Parity Check (LDPC) information bits; and an LDPC encoder configured to encode the LDPC information bits, wherein the remaining bits in which zero bits are padded include some of the bit groups which are not sequentially disposed in the LDPC information bits.

Neural networks for forward error correction decoding

Methods and apparatus for training a neural network to recover a codeword and for decoding a received signal using a neural network are disclosed. According to examples of the disclosed methods, a syndrome check is introduced at even layers of the neural network during the training, testing and online phases. During training, optimisation of trainable parameters of the neural network is ceased after optimisation at the layer at which the syndrome check is satisfied. Examples of the method for training a neural network may be implemented via a proposed loss function. During testing and online phases, propagation through the neural network is ceased at the layer at which the syndrome check is satisfied.

Retrieving data in a storage network
11513685 · 2022-11-29 · ·

A method for execution by a dispersed storage and task (DST) client module includes issuing a read threshold number of read slice requests are issued to storage units of the set of storage units. One or more encoded slices of a selected read threshold number of encoded slices are received. When a next encoded data slice of a decode threshold number of encoded data slices is received within a response timeframe, outputting of the next encoded data slice is initiated. When the next encoded data slice is not received within the response timeframe, receiving of another decode threshold number of encoded slices of the set of encoded slices is facilitated. The other decode threshold number of encoded slices are decoded to produce recovered encoded data slices, where the recovered encoded data slices includes at least a recovered next encoded data. Outputting of the recovered next encoded data slice is initiated.

Error correction decoder, error correction circuit having the same, and method of operating the same

Provided herein may be an error correction decoder, an error correction circuit having the error correction decoder, and a method of operating the error correction decoder. The error correction decoder may include a calculator configured to output an error correction message by performing an iterative decoding operation on a first codeword, a syndrome generator configured to generate a syndrome by calculating the error correction message and a parity check matrix and to output a number of iterations representing the number of times the iterative decoding operation has been performed, and an unsatisfied check node (UCN) value representing the number of unsatisfied check nodes in the syndrome, and a speed selector configured to output a speed code for controlling a speed of the iterative decoding operation depending on the number of iterations and the UCN value.

Data processing device and data processing method

The present technology relates to a data processing device and a data processing method, which are capable of securing excellent communication quality in data transmission using an LDPC code. In group-wise interleave, an LDPC code in which a code length N is 16200 bits and an encoding rate r is 10/15 or 12/15 is interleaved in units of bit groups of 360 bits. In group-wise deinterleave, a sequence of the LDPC code that has undergone the group-wise interleave is restored to an original sequence. For example, the present technology can be applied to a technique of performing data transmission using an LDPC code.

METHOD AND APPARATUS FOR LOW DENSITY PARITY CHECK CHANNEL CODING IN WIRELESS COMMUNICATION SYSTEM
20230059125 · 2023-02-23 ·

A low density parity check (LDPC) channel encoding method for use in a wireless communications system includes a communication device encoding an input bit sequence by using a LDPC matrix to obtain an encoded bit sequence for transmission. The LDPC matrix is obtained based on a lifting factor Z and a base matrix. The encoding method can be used in various communications systems including the fifth generation (5G) telecommunication systems, and can support various encoding requirements for information bit sequences with different code lengths.