An encoding method generates an encoded sequence by performing encoding of a given coding rate according to a predetermined parity check matrix. The predetermined parity check matrix is a first parity check matrix or a second parity check matrix. The first parity check matrix corresponds to a low-density parity check (LDPC) convolutional code using a plurality of parity check polynomials. The second parity check matrix is generated by performing at least one of row permutation and column permutation with respect to the first parity check matrix. An eth parity check polynomial that satisfies zero, of the LDPC convolutional code, is expressible by using a predetermined mathematical formula.

The disclosure provides a very flexible mechanism for a storage controller to create RAID stripes and to re-create corrupted stripes when necessary using the erasure coding scheme. Typically, this is known as a RAID 6 implementation/feature. The erasure code calculations are generated using the Galois Multiplication hardware and the system controller can pass any polynomial into the hardware on a per stripe calculation basis. The polynomial value is passed to the hardware via an input descriptor field. The descriptor controls the entire computation process.

In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may determine indices associated with m consecutive elements. In an aspect, each of the m consecutive elements may be associated with a different index. In addition, the apparatus may bit reverse a binary sequence associated with each of the m consecutive elements. In an aspect, each of the m consecutive elements may include a different binary sequence. Further, the apparatus may determine a bit-reversed order of the indices based at least in part on the bit-reversed binary sequence associated with each of the m elements. In addition, the apparatus may write each of the m consecutive elements to a different memory bank in parallel based at least in part on the bit-reversed order of the indices.

The present invention is directed to data communication systems and methods thereof. According to various embodiments, the present invention provides a communication with a reconfigurable forward-error-correction (FEC) module. The FEC module processes data received from two or more communication lanes, and depending on the mode of operation, the FEC module can combine data from the two or more communication lanes and perform error correction on the combined data, or the FEC module can processes data from the two communications lanes separately and perform error correction independently for the each of the data communication lanes. There are other embodiments as well.

A decoding method includes that when encoding at a sending terminal, for a m-order primitive polynomial P(x), a primitive field element in galois field GF(2.sup.m) is represented by ; a lookup table f(.sup.j) for different power exponents of is established, where the value of j is selected from all the integers ranging from 0 to 2m1, with a total number of 2m; a generator polynomial G(x) is expanded to obtain a polynomial with respect to x, with coefficients being an addition or subtraction of the power exponents of ; a remainder polynomial R(x), obtained by dividing code word polynomial Q(x) by the generator polynomial G(x), is a polynomial with respect to x, with coefficients being an addition or subtraction of the power exponents of ; and the coefficients of the generator polynomial G(x) and the remainder polynomial R(x) are both calculated using data found in the lookup table f(.sup.j).

A circuit performs a turbo detection process recovering data symbols from a received signal effected, during transmission, by a Markov process with effect that the data symbols are dependent on preceding data symbols represented as a trellis having a plurality of trellis stages. The circuit comprises processing elements, associated with trellis stages representing these dependencies and each configured to receive soft decision values corresponding to associated data symbols Each processing element configured, in one clock cycle to receive data representing a priori forward and backward state metrics, and a priori soft decision values for data symbols detected for the trellis stage. For each clock cycle of the turbo detection process, the circuit processes, for processing elements representing the trellis stages, the a priori information for associated data symbols detected for the trellis stage, and to provide extrinsic soft decision values corresponding to data symbols for a next clock cycle.

Embodiments of the present disclosure provide a high speed low latency rate configurable soft decision and hard decision based pipelined Reed-Solomon (RS) decoder architecture suitable for optical communication and storage. The proposed RS decoder is a configurable RS decoder that is configured to monitor the channel and adjust code parameters based on channel capacity. The proposed RS decoder includes interpolation and factorization free Low-Complexity-Chase (LCC) decoding to implement soft-decision decoder (SDD). The proposed RS decoder generates test vectors and feeds these to a pipelined 2-stage hard decision decoder (HDD). The proposed RS decoder architecture computes error locator polynomial in exactly 2t clock cycles without parallelism and supports high throughput, and further computes error evaluator polynomial in exactly t cycles. The present disclosure provides a 2-stage pipelined decoder to operate at least latency possible and reduced size of delay buffer.

A signal processor including a Pulse Width Modulation (PWM) encoder configured to encode data into a data PWM pattern; and a block encoder coupled to the PWM encoder, and configured to determine a checksum of the data PWM pattern, wherein the PWM encoder is further configured to encode the checksum into a checksum PWM pattern, and append the checksum PWM pattern on the data PWM pattern for transmission as a PWM signal.

Bits in a received word that is based on a codeword of a polar code are decoded to generate decoded bits. A lower-order partial sum is updated based on the decoded bits, and a higher-order partial sum based on the lower-order partial sum is computed. The higher-order partial sum computation is a live computation performed during decoding of a subsequent bit in the received word in some embodiments. In decoding the subsequent bit, nodes in a Data Dependency Graph (DDG) of the polar code may be traversed in a reverse order relative to node indices of at least some of the nodes in the DDG. A reverse order may also be applied to partial sum computations, to combine multiple lower-order partial sums that are based on previously decoded bits according to a reverse order relative to an order in which at least some of the previously decoded bits were decoded.

A method for generating a binary GTP codeword, comprised of N structure stages and each stage comprises at least one BCH codeword with error correction capability greater than a prior stage and smaller than a next stage, includes: receiving a syndrome vector s of a new stage 0 binary BCH codeword y over a field GF(2.sup.m) that comprises t syndromes of length m bits, wherein the syndrome vector s comprises l-th Reed-Solomon (RS) symbols of t RS codewords whose information symbols are delta syndromes of all BCH codewords from stage 0 until stage n1; and multiplying s by a right submatrix of a matrix U, wherein U is an inverse of a parity matrix of an BCH code defined by t.sub.n, wherein the new binary BCH codeword is y=.Math.s.