A method of making a fusion bonded circuit structure. Each major surface of an LCP substrate is provided with a seed layers of a conductive material. Resist layers are deposited on the seed layers. The resist layers are processed to create recesses corresponding to a desired circuitry layers on each side of the LCP substrate. The recesses expose portions of the seed layers of conductive material. The LCP substrate is electroplated to simultaneously create conductive traces defined by the first recesses on both sides of the LCP substrate. The resist layers are removed to reveal the conductive traces. The LCP substrate is etched to remove exposed portions of the seed layers adjacent the conductive traces. LCP layers are fusion bonded to the major surfaces of the LCP substrate to encapsulate the conductive traces in an LCP material. The LCP layers can be laser drilled to expose the conductive traces.

Provided are a pattern formation method including a step of preparing a base material which has an etching layer transparent to an exposure wavelength on each of two surfaces thereof and is transparent to the exposure wavelength, a step of forming a photosensitive resin layer, in which an optical density to the exposure wavelength is in a range of 0.50 to 2.50, on the etching layer on each of the two surfaces of the base material, a step of pattern-exposing the photosensitive resin layer, a step of developing the photosensitive resin layer to form a resist pattern on two surfaces, a step of removing the etching layer on a portion that is not coated with the resist pattern, and a step of peeling the resist pattern off, in this order, a laminate, and a method of producing a touch panel.

A method of manufacturing a component carrier is disclosed. The method includes forming a stack having at least one electrically conductive layer structure and/or at least one electrically insulating layer structure; patterning a front side of the stack using a first photo-imageable dielectric; and patterning a back side of the stack. A component carrier is also disclosed.

A photosensitive resin composition comprises: a resin having a phenolic hydroxyl group; a photosensitive acid generator; a compound having at least one selected from the group consisting of an aromatic ring, a heterocycle and an alicycle, and at least one selected from the group consisting of a methylol group and an alkoxyalkyl group; and an aliphatic compound having two or more functional groups, the functional groups being at least one functional group selected from the group consisting of an acryloyloxy group, a methacryloyloxy group, a glycidyloxy group, an oxetanyl alkyl ether group, a vinyl ether group and a hydroxyl group, wherein the photosensitive acid generator is a sulfonium salt containing an anion having at least one skeleton selected from the group consisting of a tetraphenylborate skeleton, an alkylsulfonate skeleton having 1 to 20 carbon atoms, a phenylsulfonate skeleton and a 10-camphorsulfonate skeleton.

A printed circuit board includes an insulating material and a circuit, formed on a surface of the insulating material. The circuit comprises a seed layer formed on the surface of the insulating material, an anti-reflection layer formed on the seed layer, and an electroplating layer formed on the anti-reflection layer.

A composite circuit board includes an insulation layer, an inner circuit layer, a first conductive layer and a second conductive layer embedded in the insulation layer, a third conductive layer and a fourth conductive layer formed on opposite surfaces of the insulation layer. The third conductive layer electrically connects with the first conductive layer. The fourth conductive layer electrically connects with the second conductive layer. The inner circuit layer is in a middle portion of the insulation layer. The first conductive layer and the second conductive layer respectively forms on opposite sides of the inner circuit layer. The insulation layer forms a plurality of first through holes between the first conductive layer and the inner circuit layer, a plurality of second through holes between the second conductive layer and the inner circuit layer.

A method for manufacturing a substrate structure is provided. The method includes the following steps. A substrate is provided. The substrate has a patterned first metal layer, a pattern second metal layer and a through hole. After that, a first dielectric layer and a second dielectric layer are formed at a first surface and a second surface of the substrate, respectively. The second surface is opposite to the first surface. Then, the first dielectric layer and the second dielectric layer are patterned. After that, a first trace layer is formed at a surface of the patterned first dielectric layer. The first trace layer is embedded into the patterned first dielectric layer and is coplanar with the first dielectric layer. Then, a second trace layer is formed on a surface of the second dielectric layer.

Methods and systems are contemplated for making portions of electrical circuits with embedded electrical components, and the electrical circuits produced thereby. A layer of dielectric material is deposited over a substrate, and a cavity is formed in the dielectric material. An electrical component (e.g., integrated chip, etc.) is deposited in the cavity and covered by a further dielectric material, embedding the electrical component. Another cavity is formed in the further dielectric material, and a catalyst (e.g., electrolytic deposition catalyst, electroless deposition catalyst, etc.) is deposited over the further dielectric material and at least a portion of the electrical component. A conductor is then plated at the catalyst, preferably contacting the I/O ports of the electrical component.

An asymmetric electronic substrate and method of making the substrate includes forming a first layer on each opposing major surface of a removable carrier layer, the first layer being a routing layer, simultaneously laminating the first layers, and building up subsequent layers on layers previously formed and laminated on the removable carrier layer iteratively. The subsequent layers including routing layers and a core layer formed on each side of the removable carrier layer, the core layer including through holes having a larger gauge than through holes included in the routing layers. A number of layers on a first side of the core layer, between the core layer and the carrier layer, is different than a number of layers on a second side of the core layer. The carrier layer is removed to produce two asymmetric substrates, each asymmetric substrate including one of the at least one core layers.

Disclosed is a method of manufacturing a wiring board, which allows a desmearing process to be carried out appropriately without roughening a surface of an insulating layer. The method of manufacturing a wiring board includes a light irradiation step for irradiating a wiring board material with ultraviolet light in an atmosphere containing oxygen. The wiring board material has an insulating layer laminated on a conductive layer, a protective layer formed on the insulating layer, and a through hole (viahole) that penetrates the insulating layer and the protective layer. The method also includes a plating step for forming a plating layer, which is made from a conductive material, on the surface of the wiring board material from which the protective layer has been removed. The surface of the wiring board material includes a bottom of the through hole.