The present invention comprises a step of forming bump pads on the surface of the substrate, covering the whole surface with a second insulating layer, forming a copper barrier on the surface of a second insulating layer, forming a third insulating layer, and forming a copper layer for an electrical circuit. A mask is formed on the copper layer of the external circuit in such a way that only the region for the cavity is exposed. The cavity is formed by laser-drilling only the surface-exposed area of the third insulating layer. The copper layer at the bottom protects the second insulating layer and bump pads underneath from laser damages. The copper barrier is removed by chemical etch once the laser drill is over. The second insulating layer will be removed via sand blast process, exposing the bump pads which were fabricated in the earlier steps.

A printer deposits material onto a substrate as part of a manufacturing process for an electronic product; at least one transported component experiences error, which affects the deposition. This error is mitigated using transducers that equalize position of the component, e.g., to provide an “ideal” conveyance path, thereby permitting precise droplet placement notwithstanding the error. In one embodiment, an optical guide (e.g., using a laser) is used to define a desired path; sensors mounted to the component dynamically detect deviation from this path, with this deviation then being used to drive the transducers to immediately counteract the deviation. This error correction scheme can be applied to correct for more than type of transport error, for example, to correct for error in a substrate transport path, a printhead transport path and/or split-axis transport non-orthogonality.

A multi-layer line structure including a substrate, a lower layer Cu line located on the substrate, an upper layer Cu line located on an insulating layer including an inorganic film located on the lower layer Cu line and an organic resin film located on the inorganic film, and a via connection part located in a via connection hole running in an up-down direction through the insulating layer in an area where the lower layer Cu line and the upper layer Cu line overlap each other is provided. The via connection part includes a barrier conductive layer located on a part of the lower layer Cu line exposed to a bottom part of the via connection hole and on an inner wall of the via connection hole.

In multilayer circuit substrate wiring patterns and reference marks are formed on an upper surface of each insulating layer in a predetermined positional relationship, and the reference marks on the insulating layers are formed at overlapping positions when viewed from above. Furthermore, the reference mark on each layer is formed by changing a size or a shape such that from a specific edge portion recognized when center coordinates of the reference mark is detected by image processing a specific edge portion of the reference mark on a lower layer of the specific edge portion does not protrude considering a positional deviation at the time of manufacturing. The multiple insulating layers are formed of an insulating material having light transparency or an insulating material designed to be extremely thin so that a lower layer can be seen through even if the light transparency is poor.

A method for manufacturing a circuit board circuit board for transmitting high-frequency signal, including: providing a first-line circuit board (20), a second circuit board (40), at least one third circuit board (50), a fourth circuit board (60), a fifth circuit board (61), and a sixth circuit board (62); stacking the first circuit board (20), the second circuit board (40), and third circuit board (50) in that order, and stacking the fourth circuit board (60), the sixth circuit board (62), and the fifth circuit board (61) on the third circuit board (50), and pressing them together to obtain the circuit board circuit board for transmitting high-frequency signal. The method manufacturing the circuit board circuit board for transmitting high-frequency signal can reduce a width of the transmission line. The present disclosure further provides the circuit board circuit board for transmitting high-frequency signal obtained by the above method.

A circuit board structure for a display device includes a substrate, a bump, a protective layer, and a moisture-resistant layer. The substrate includes a first surface and a second surface opposite to the first surface. The bump is disposed on the first surface of the substrate and includes a first inorganic material. The protective layer is disposed on the first surface of the substrate. The protective layer includes an organic material and a first opening, in which the bump is positioned in the first opening. The moisture-resistant layer entirely covers the protective layer. The moisture-resistant layer includes a second inorganic material and a second opening, in which a portion of the bump is exposed in the second opening.

A package carrier includes a circuit structure layer and a heat-conducting element. The circuit structure layer includes a notch portion. The heat-conducting element includes a first heat-conducting portion and a second heat-conducting portion vertically connected to the first heat-conducting portion. The notch portion exposes the first heat-conducting portion, and an outer surface of the second heat-conduction portion is aligned with a side surface of the circuit structure layer.

Embodiments of present invention provide a multilayer printed circuit board. The printed circuit board includes a first conducting layer (CL) having a first measurement mark area (MMA) and a second CL having a second MMA. A first polygonal measurement mark (MM) in the first MMA and a second and a third polygonal MM in the second MMA, wherein the second polygonal MM is positioned along an extended first angle bisector bisecting a first vertex of the first polygonal MM and a first vertex of the second polygonal MM is substantially aligned with the first vertex of the first polygonal MM, and wherein the third polygonal MM is positioned along an extended second angle bisector bisecting a second vertex of the first polygonal MM and a first vertex of the third polygonal MM is substantially aligned with the second vertex of the first polygonal MM.

A printer deposits material onto a substrate as part of a manufacturing process for an electronic product; at least one transported component experiences error, which affects the deposition. This error is mitigated using transducers that equalize position of the component, e.g., to provide an “ideal” conveyance path, thereby permitting precise droplet placement notwithstanding the error. In one embodiment, an optical guide (e.g., using a laser) is used to define a desired path; sensors mounted to the component dynamically detect deviation from this path, with this deviation then being used to drive the transducers to immediately counteract the deviation. This error correction scheme can be applied to correct for more than type of transport error, for example, to correct for error in a substrate transport path, a printhead transport path and/or split-axis transport non-orthogonality.

A multi-layer line structure including a substrate, a lower layer Cu line located on the substrate, an upper layer Cu line located on an insulating layer including an inorganic film located on the lower layer Cu line and an organic resin film located on the inorganic film, and a via connection part located in a via connection hole running in an up-down direction through the insulating layer in an area where the lower layer Cu line and the upper layer Cu line overlap each other is provided. The via connection part includes a barrier conductive layer located on a part of the lower layer Cu line exposed to a bottom part of the via connection hole and on an inner wall of the via connection hole.