A method of manufacturing a semiconductor device includes forming a lower mold having lower layers stacked on a substrate and lower channel structures passing therethrough; forming an upper mold including upper layers stacked on the lower mold and upper channel structures passing therethrough; removing the upper mold to expose an upper surface of the lower mold; separating an upper original image in which traces of the upper channel structures are displayed, and a lower original image in which the lower channel structures are displayed, from an original image capturing the upper surface of the lower mold; inputting the upper original image into a learned neural network to acquire an upper restored image in which cross sections of the upper channel structures are displayed; and comparing the upper restored image with the lower original image to verify an alignment state of the upper and lower molds.

An integrated circuit device includes: a substrate including a plurality of active regions; a bit line extending on the substrate in a horizontal direction; a direct contact connected between a first active region selected among the plurality of active regions and the bit line; an inner oxide layer contacting a sidewall of the direct contact; and a carbon-containing oxide layer nonlinearly extending on a sidewall of the bit line in a vertical direction, the carbon-containing oxide layer contacting the sidewall of the bit line.

The present disclosure provides a semiconductor structure having a fin structure. The semiconductor includes a substrate defined with an active region. A first gate structure is disposed in the active region and includes a dielectric material. A second gate structure is disposed in the active region and includes the dielectric material. A fin structure having a first top surface is arranged to alternate with the first gate structure and the second gate structure. The first gate structure has a second top surface and the second gate structure has a third top surface. The second top surface and the third top surface are lower than the first top surface.

A capacitor includes a lower electrode including a first metal material and having a first crystal size in a range of a few nanometers, a dielectric layer covering the lower electrode and having a second crystal size that is a value of a crystal expansion ratio times the first crystal size and an upper electrode including a second metal material and covering the dielectric layer. The upper electrode has a third crystal size smaller than the second crystal size.

Some embodiments include a memory device having a buried wordline, a shield plate, and an access device. The access device includes first and second diffusion regions and a channel region. The diffusion regions and the channel region are arranged vertically so that the channel region is between the first and second diffusion regions. The wordline is adjacent to a first side surface of the channel region, and the shield plate is adjacent to a second side surface of the channel region; with the first and second side surfaces being in opposing relation to one another. Some embodiments include methods of forming integrated assemblies.

A method of manufacturing a memory structure is provided. The method includes forming a first gate structure, a second gate structure, and a plurality of source/drain regions in a substrate, in which the plurality of source/drain regions are disposed on opposite sides of the first gate structure and the second gate structures; performing a dry etching process to form a trench between the first gate structure and the second gate structure; performing a wet etching process to expand the trench, in which the expanded trench has a hexagonal shaped cross section profile; and forming a bit line contact in the expanded trench.

The present disclosure relates to a method for preparing a semiconductor device with air gaps between conductive lines (e.g., bit lines). The method includes forming a first dielectric structure and a second dielectric structure over a semiconductor substrate, and forming a conductive material over the first dielectric structure and the second dielectric structure. The conductive material extends into a first opening between the first dielectric structure and the second dielectric structure. The method also includes partially removing the conductive material to form a first bit line and a second bit line in the first opening and forming a sealing dielectric layer over the first bit line and the second bit line such that an air gap is formed between the sealing dielectric layer and the semiconductor substrate.

Semiconductor devices may include an active pattern, a gate structure in an upper portion of the active pattern, a bit line structure on the active pattern, a lower spacer structure on a lower portion of a sidewall of the bit line structure, and an upper spacer structure on an upper portion of the sidewall of the bit line structure. The lower spacer structure includes first and second lower spacers sequentially stacked, the first lower spacer contacts the lower portion of the sidewall of the bit line structure and does not include nitrogen, and the second lower spacer includes a material different from the first lower spacer. A portion of the upper spacer structure contacting the upper portion of the sidewall of the bit line structure includes a material different from the first lower spacer.

A method for forming a semiconductor device includes the following operations. A stacked structure is provided, which includes a substrate, and sacrificial layers and semiconductor layers alternately stacked on surface of the substrate. Multiple first grooves and semiconductor pillars extending in first direction are included in the sacrificial layers and the semiconductor layers. Word line pillars are formed in second direction, intersect with the semiconductor pillars and surround the semiconductor pillars. Sources and drains are formed respectively on either side of the semiconductor pillars surrounded by the word line pillars by an epitaxial growth process. Bit lines are formed on a side of the sources or the drains, are connected with same, and extend in third direction. The first, second and third directions are pairwise perpendicular. Capacitors are formed on a side of the sources or the drains where the bit lines are not formed to form a semiconductor device.

Embodiments provide a method for fabricating a semiconductor structure and a structure thereof. The method includes: providing a substrate; forming, on the substrate, semiconductor channels arranged in an array along a first direction and a second direction; forming bit lines extending along the first direction, wherein the bit lines are positioned in the substrate, and each of the bit lines is electrically connected to the semiconductor channels arranged along the first direction; forming word lines extending along the second direction, wherein the word lines wrap part of side surfaces of the semiconductor channels arranged along the second direction, where one of the word lines includes two sub word lines arranged at intervals along the first direction, and the sub word lines cover part of opposite side surfaces of the semiconductor channels along the first direction; and forming isolation structures positioned between adjacent word lines and between adjacent sub word lines.