Embodiments provide a semiconductor structure and a method for fabricating the same. The semiconductor structure includes: a substrate; bit lines positioned in the substrate, where each of the bit lines includes a conductive body and a dielectric layer, the conductive body includes a body portion and a plurality of contact portions, the body portion extend along a first direction, the contact portions protrude from a side surface of the body portion facing away from a bottom of the substrate, the contact portions are arranged at intervals along the first direction, and the dielectric layer covers side wall surfaces on left and right sides of the body portion along an extension direction; and transistors positioned on top surfaces of the contact portions facing away from the body portion, and extension directions of channels of the transistors are perpendicular to a plane where the substrate is positioned.

Embodiments provide a semiconductor structure and a method thereof. The method includes: providing a first substrate, and forming a drive pad on the first substrate; providing a second substrate, and forming active pillars and a bit line in sequence on a side of the second substrate, wherein a side of the bit line is connected to the active pillars, and a surface of the bit line facing away from the active pillars is exposed on a surface of the second substrate; bonding the bit line to the drive pad correspondingly; thinning the second substrate from a side of the second substrate facing away from the first substrate until the active pillars are exposed; and forming a storage capacitor on sides of the active pillars facing away from the drive pad, the storage capacitor being connected to the active pillars.

Embodiments provide a semiconductor structure and a formation method thereof. The semiconductor structure includes: a substrate provided with semiconductor pillars arranged at intervals, the semiconductor pillars including a first doped region, a channel region and a second doped region sequentially arranged along a direction distant from a surface of the substrate; and a plurality of word lines extending along a first direction and an insulating layer between adjacent word lines. Each word line surrounds the channel region of the semiconductor pillars arranged along the first direction, and along the direction distant from the surface of the substrate, a width of the insulating layer perpendicular to the first direction gradually decreases. The embodiments are at least advantageous to ensuring that the word lines have better continuity.

A semiconductor structure and a method for manufacturing same. The semiconductor structure includes a storage unit, which includes: a first dielectric layer and a metal bit line located therein; a semiconductor channel, located on the metal bit line; a word line, disposed surrounding part of the semiconductor channel; a second dielectric layer, located between the metal bit line and the word line, and on top of the word line; a first and a second lower electrode layers, stacked on the semiconductor channel, the first lower electrode layer contacting the top surface of the semiconductor channel; an upper electrode layer, located on top of the second lower electrode layer, and surrounding the first and the second lower electrode layers; and a capacitor dielectric layer, located between the upper electrode layer and the first lower electrode layer, and between the upper electrode layer and the second lower electrode layer.

Embodiments relate to a semiconductor device and a forming method. The semiconductor device includes: a substrate; a memory array positioned on the substrate and at least including memory cells spaced along a first direction, each of the memory cells including a transistor, the transistor including a gate electrode, channel regions distributed on two opposite sides of the gate electrode along a third direction, and a source region and a drain region distributed on two opposite sides of each of the channel regions along a second direction, the first direction and the third direction being directions parallel to a top surface of the substrate, the first direction intersecting with the third direction, and the second direction being a direction perpendicular to the top surface of the substrate; and a word line extending along the first direction and continuously electrically connected to the gate electrodes spaced along the first direction.

A semiconductor structure and a method for manufacturing the same, and a memory are provided. The semiconductor structure includes: a substrate, a plurality of oxide pillars, a plurality of active pillars, a first insulating layer and a storage structure. The plurality of oxide pillars are on the substrate and arranged in an array along a first direction and a second direction. Both the first direction and the second direction are parallel to a surface of the substrate, and the first direction intersects with the second direction. The first insulating layer is in a gap between the oxide pillars. Each active pillar is on a top surface of a corresponding one of the oxide pillars. The storage structure covers at least part of a side wall of the active pillar.

A semiconductor device includes a plurality of bit line structures formed to be spaced apart from each other over a semiconductor substrate, a first spacer formed on both sidewalls of each of the bit line structures, a lower plug formed between the bit line structures and in contact with the semiconductor substrate, an upper plug positioned over the lower plug and having a greater line width than the lower plug, a middle plug positioned between the lower plug and the upper plug and having a smaller line width than a line width of the lower plug, and a second spacer positioned between the middle plug and the first spacer, wherein the second spacer is thicker than the first spacer.

A semiconductor structure and a method for forming a semiconductor structure are provided. The method includes: a substrate is provided; bit line contact holes spaced apart from each other, bit line contacts each in contact with a part of a respective one of the bit line contact holes, and bit line structures are formed on the substrate, where each of the bit line structures includes at least a conductive layer and an insulating cap layer, and the insulating cap layer is located on the conductive layer; first insulating layers completely filling the bit line contact holes are formed inside the bit line contact holes; and insulation structures with air interlayers are formed on two side walls of the bit line structures, where a height of each of the air interlayers is greater than a height of the conductive layer of each of the bit line structures.

Embodiments of the disclosure provide a semiconductor substrate, a method for forming same, and a layout structure. The method includes: providing a semiconductor structure including a first region and a second region arranged in sequence along a second direction, the second region including active structures arranged in an array along a first direction and a third direction, each of the active structure at least including a channel structure, the first direction, the second direction, and the third direction being perpendicular to each other, and the first direction and the second direction being parallel to a surface of the semiconductor substrate; forming a gate structure on a surface of the channel structure; and forming a word line structure extending in the first direction on the first region. The word line structure is connected with the gate structure located on the same layer.

A semiconductor structure includes: a substrate; bit lines located in the substrate and including a main body and a plurality of contact portions, the main body extending in a first direction, the contact portions being connected to the main body and extending toward the top surface of the substrate, and the plurality of contact portions being arranged at intervals in the first direction; and transistors located on a top surface of the contact portion, the extension direction of a channel of the transistor being perpendicular to a plane where the substrate is located.