A semiconductor wafer includes a silicon carbide wafer and an epitaxial layer, which is disposed at a surface of the silicon carbide wafer and made of silicon carbide. The semiconductor wafer satisfies a condition that a waviness value is equal to or smaller than 1 micrometer. The waviness value is a sum of an absolute value of a value α and an absolute value of a value β. A highest height among respective heights of a plurality of points with reference to a surface reference plane within a light exposure area is denoted as the value α. A lowest height among the respective heights of the points at the epitaxial layer with reference to the surface reference plane within the light exposure area is denoted as the value β.

A method for manufacturing a carrier substrate on a semiconductor wafer that includes a front side and a rear side, the front side being situated opposite the rear side, the front side representing a structured semiconductor wafer side including contact areas. The method includes the following steps: applying at least one first layer to the front side with the aid of printing technology, the at least one first layer including a first material that is water-insoluble, and curing the at least one first layer with the aid of UV radiation, thermally or with the aid of sintering.

A stacking structure is applicable to manufacturing a circuit board. The stacking structure includes a transferring layer and a dielectric layer disposed on the transferring layer. The transferring layer includes a substrate and a thin film disposed on the substrate and having a plurality of recess structures thereon. The recess structures are connected as a single piece and bottom portions and top portions of the recess structures are configured to arrange in a staggered manner to form a multi-dimensional arrangement. At least a portion of the dielectric layer being is located in the recess structures, such that the dielectric layer is at least embedded with the recess structures.

A method includes etching a silicon layer in a wafer to form a first trench in a first device region and a second trench in a second device region, performing a pre-clean process on the silicon layer, performing a baking process on the wafer, and performing an epitaxy process to form a first silicon germanium region and a second silicon germanium region in the first trench and the second trench, respectively. The first silicon germanium region and the second silicon germanium region have a loading in a range between about 5 nm and about 30 nm.

A bonding wafer structure includes a support substrate, a bonding layer, and a silicon carbide (SiC) layer. The bonding layer is formed on a surface of the support substrate, and the SiC layer is bonded onto the bonding layer, in which a carbon surface of the SiC layer is in direct contact with the bonding layer. The SiC layer has a basal plane dislocation (BPD) of 1,000 ea/cm.sup.2 to 20,000 ea/cm.sup.2, a total thickness variation (TTV) greater than that of the support substrate, and a diameter equal to or less than that of the support substrate. The bonding wafer structure has a TTV of less than 10 μm, a bow of less than 30 μm, and a warp of less than 60 μm.

An electronic substrate includes a dielectric core, a first conducting layer on a first side of the core and a second conducting layer on the second side of the core opposite the first side. At least one differential coaxial through-via includes a first inner signal through-via that is at least electrical conductor lined for a first signal path and at least a second inner signal through-via that is also at least electrical conductor lined positioned side-by-side and being dielectrically isolated from the first inner signal through-via for a second signal path. An annular-shaped outer ground shield enclosure is at least conductor lined that surrounds and is dielectrically isolated from both the first and second inner signal through-vias.

A compound semiconductor laminate substrate comprising two single-crystalline compound semiconductor substrates directly bonded together and laminated, the single-crystalline compound semiconductor substrates having the same composition including A and B as constituent elements and having the same atomic arrangement, characterized in that the front and back surfaces of the laminate substrate are polar faces comprising the same kind of atoms of A or B, and that a laminate interface comprises a bond of atoms of either B or A and is a unipolar anti-phase region boundary plane in which the crystal lattices of the atoms are matched. In this way, the polar faces of the front and rear surfaces of the compound semiconductor laminate substrate are made monopolar, thereby facilitating semiconductor element process designing, and making it possible to manufacture a low-cost, high-performance, and stable semiconductor element without implementing complex substrate processing.

A method is disclosed for promoting the formation of uniform platelets in a monocrystalline semiconductor donor substrate by irradiating the monocrystalline semiconductor donor substrate with light. The photon-absorption assisted platelet formation process leads to uniformly distributed platelets with minimum built-in stress that promote the formation a well-defined cleave-plane in the subsequent layer transfer process.

A method includes moving a drum containing a chemical liquid into a chamber of a chemical liquid supplying system. The drum is connected with a testing pipe. The chemical liquid is pumped from the drum to the testing pipe. A condition of the chemical liquid flowing through the testing pipe is monitored. Whether the chemical liquid is supplied to a processing tool is determined based on the condition of the chemical liquid.

A method for manufacturing a gallium nitride semiconductor device includes: preparing a gallium nitride wafer; forming an epitaxial growth film on the gallium nitride wafer to provide a processed wafer having chip formation regions; perform a surface side process on a one surface side of the processed wafer; removing the gallium nitride wafer and dividing the processed wafer into a chip formation wafer and a recycle wafer; and forming an other surface side element component on an other surface side of the chip formation wafer.