The present application relates to a block copolymer and uses thereof. The present application can provide a block copolymer—which exhibits an excellent self-assembling property and thus can be used effectively in a variety of applications—and uses thereof.

A method of cyclic etching, comprising: (A) depositing, prior to cyclically etching a substrate through a mask opening, a pre-etch protection layer conformally over the mask, sidewalls of the mask defining the mask opening; and an exposed portion of the substrate exposed through the mask opening, the pre-etch protection layer deposited to a first thickness; and (B) cyclically etching the substrate by: (i) depositing a protection layer in the opening of the mask, the protection layer deposited to a second thickness that is less than half of the first thickness; (ii) etching through a portion of the protection layer disposed on the substrate and etching the substrate; and (iii) repeating (i) and (ii) until an end point is reached.

A method of patterning a photoresist layer includes forming a photoresist layer on a substrate, exposing the photoresist layer to light using a first light source so as to induce a chemical change in the photoresist layer, performing a post-exposure bake process on the photoresist layer, the post-exposure bake process including irradiating the photoresist layer with at least two shots of laser light from a second light source such that the photoresist layer is heated to a first temperature, and performing a developing process on the photoresist layer after the post-exposure bake process, the development process selectively removing a portion of the photoresist layer.

Methods for selectively forming a target film on a substrate comprising a first dielectric surface and a second metallic surface are disclosed. The methods may include: contacting the substrate with a plasma generated from a hydrogen containing gas, selectively forming a passivation film from vapor phase reactants on the first dielectric surface while leaving the second metallic surface free from the passivation film, and selectively depositing the target film from vapor phase reactants on the second metallic surface relative to the passivation film.

A method for forming a film with an annealing step and a deposition step is disclosed. The method comprises an annealing step for inducing self-assembly or alignment within a polymer. The method also comprises a selective deposition step in order to enable selective deposition on a polymer.

A method of fabricating a semiconductor device is disclosed. The method includes forming a dielectric layer over a substrate. The substrate has an edge region and a center region. The method also includes forming a dielectric ring in the edge region, forming a metal layer over the center region of the substrate and over the dielectric ring in the edge region of the substrate and polishing the metal layer in the center region and the edge region to expose the dielectric ring in the edge region of the substrate.

Various patterning methods involved with manufacturing semiconductor devices are disclosed herein. A method for fabricating a semiconductor structure (for example, interconnects) includes forming a patterned photoresist layer over a dielectric layer. An opening (hole) is formed in the patterned photoresist layer. In some embodiments, a surrounding wall of the patterned photoresist layer defines the opening, where the surrounding wall has a generally peanut-shaped cross section. The opening in the patterned photoresist layer can be used to form an opening in the dielectric layer, which can be filled with conductive material. In some embodiments, a chemical layer is formed over the patterned photoresist layer to form a pair of spaced apart holes defined by the chemical layer, and an etching process is performed on the dielectric layer using the chemical layer as an etching mask to form a pair of spaced apart holes through the dielectric layer.

The disclosure provides a thin film transistor, an array substrate, and a method for fabricating the same. An embodiment of the disclosure provides a method for fabricating a thin film transistor, the method including: forming a gate, a gate insulation layer, and an active layer above an underlying substrate successively; forming a patterned hydrophobic layer above the active layer, wherein the hydrophobic layer includes first pattern components, and orthographic projections of the first pattern components onto the underlying substrate overlap with a orthographic projection of a channel area at the active layer onto the underlying substrate; and forming a source and a drain above the hydrophobic layer, wherein the source and the drain are located respectively on two sides of a channel area, and in contact with the active layer.

An n-type metal-oxide-semiconductor (NMOS) transistor comprises a graphene channel with a chemically adsorbed nitrogen dioxide (NO.sub.2) layer formed thereon. The NMOS transistor may comprise a substrate having a graphene layer formed thereon and a gate stack formed on a portion of the graphene layer disposed in a channel region that further includes a spacer region. The gate stack may comprise the chemically adsorbed NO.sub.2 layer formed on the graphene channel, a high-k dielectric formed over the adsorbed NO.sub.2 layer, a gate metal formed over the high-k dielectric, and spacer structures formed in the spacer region. The adsorbed NO.sub.2 layer formed under the gate and the spacer structures may therefore attract electrons from the graphene channel to turn the graphene-based NMOS transistor off at a gate voltage (V.sub.g) equal to zero, making the graphene-based NMOS transistor suitable for digital logic applications.

A pattern forming method which uses a resist underlayer film having resistance to a basic aqueous hydrogen peroxide solution. A pattern forming method including: a first step of applying a resist underlayer film-forming composition containing a solvent and a polymer having a weight average molecular weight of 1,000 to 100,000 and an epoxy group on a semiconductor substrate that may have an inorganic film on the surface, followed by baking, to form a resist underlayer film; a second step of forming a resist pattern on the resist underlayer film; a third step of dry etching the resist underlayer film using the resist pattern as a mask to expose a surface of the inorganic film or the semiconductor substrate; and a fourth step of wet etching the inorganic film or the semiconductor substrate using the dry-etched resist underlayer film as a mask and a basic aqueous hydrogen peroxide solution.