Patent classifications
H01L21/0273
STAIRCASE STRUCTURE FOR MEMORY DEVICE
A semiconductor structure is disclosed. The semiconductor structure includes a staircase structure disposed over a substrate. The staircase structure includes a plurality of layer stacks, where each layer stack is made of a first material layer over a portion of a second material layer. The staircase structure further includes a plurality of landing pads, where each landing pad is disposed over another portion of the second material layer of a respective layer stack.
Substrate processing method and apparatus
Provided are a substrate processing apparatus and a substrate processing method capable of achieving uniform trimming throughout an entire surface of a substrate. The substrate processing apparatus includes a gas channel including a center gas inlet and an additional gas inlet spaced apart from the center gas inlet, and a shower plate including a plurality of holes connected to the center gas inlet and the additional gas inlet, wherein a gas flow channel is formed having a clearance defined by a lower surface of the gas channel and an upper surface of the shower plate, the lower surface and the upper surface being substantially parallel.
Hybrid Development of EUV Resists
A method of microfabrication includes depositing a photoresist film on a working surface of a semiconductor wafer, the photoresist film being sensitive to extreme ultraviolet radiation; exposing the photoresist film to a pattern of extreme ultraviolet radiation; performing a hybrid develop of the photoresist film. The hybrid develop includes executing a first development process to remove a first portion of the photoresist film; stopping the development of the photoresist film after the first development process, the photo resist film including a structure having a first critical dimension larger than a target critical dimension after the stopping; and after stopping the development, executing a second development process to remove a second portion of the photoresist film and shrinking the critical dimension of the structure from the first critical dimension to a second critical dimension that is less than the first critical dimension.
METAL ETCHING WITH IN SITU PLASMA ASHING
An apparatus for perform metal etching and plasma ashing includes: a processing chamber having an enclosed area; an electrostatic chuck disposed in the enclosed area and configured to secure a wafer, the electrostatic chuck connected with a bias power; at least one coil connected with a source power; a etchant conduit configured provide an etchant to a metal of the wafer within the processing chamber in accordance with a photoresist mask of the wafer; and a gas intake conduit connected with a gas source, wherein the gas intake conduit is configured to supply the processing chamber with a gas from the gas source during performance of plasma ashing within the processing chamber.
SEMICONDUCTOR STRUCTURE, METHOD FOR MANUFACTURING SAME AND MEMORY
A semiconductor structure, a method for manufacturing the same and a memory are provided. The semiconductor structure at least includes two photolithography layers which are arranged in sequence and at least one blocking layer. Each photolithography layer includes a functional pattern and an overlay mark, and the photolithography layers include a first photolithography layer and a second photolithography layer. The first photolithography layer includes a first functional pattern and a first overlay mark, and the second photolithography layer includes a second functional pattern and a second overlay mark; and at least one blocking layer. The blocking layer is located between the first functional pattern and the second functional pattern, and a vertical distance between the first functional pattern and the second functional pattern is greater than a vertical distance between the first and second overlay marks, in a stacking direction of the photolithography layers.
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A method of manufacturing a semiconductor device, the method including forming a lower film on a substrate; forming a metal-containing photoresist material film on the lower film; patterning the metal-containing photoresist material film to form a photoresist pattern including openings therein such that a scum remains on the lower film; performing a descum operation to remove the scum from the lower film; and etching the lower film using the photoresist pattern, wherein performing the descum operation includes providing the substrate to a processing chamber; generating oxygen plasma; and reacting the scum with the oxygen plasma.
METHOD OF FABRICATING SEMICONDUCTOR DEVICE INCLUDING POROUS DIELECTRIC LAYER AND SEMICONDUCTOR DEVICE FABRICATED THEREBY
A method of fabricating a semiconductor device and a device fabricated thereby, the method including sequentially stacking an interlayer insulating layer, a porous dielectric layer, a first mask layer, and a second mask layer on a substrate; etching the second mask layer to form preliminary mask patterns; etching the preliminary mask patterns to form second mask patterns; etching the first mask layer using the second mask patterns as an etch mask to form first mask patterns; etching the porous dielectric layer using the first mask patterns as an etch mask to form grooves; and forming interconnection patterns in the grooves, respectively, wherein the porous dielectric layer includes SiOCH, and the first mask layer includes carbon-free silicon oxide (SiO.sub.2).
Method of forming pattern of cured product as well as production methods for processed substrate, optical component, circuit board, electronic component, imprint mold and imprint pretreatment coating material
Provided is a method of producing a cured product pattern, including: a first step (arranging step) of arranging a layer formed of a curable composition (α1′) that is the components of the curable composition (α1) except the component (D) serving as a solvent on a substrate; and a second step (applying step) of applying droplets of a curable composition (α2) discretely onto the layer formed of the curable composition (α1), the curable composition (α1) having a number concentration of particles each having a particle diameter of 0.07 μm or more of less than 2,021 particles/mL, and the curable composition (α1′) having a surface tension larger than that of the curable composition (α2).
Imprint apparatus, imprint method, and article manufacturing method
An imprint apparatus includes a deforming mechanism for deforming a pattern region of a mold, and performs, after first processing for applying a first deformation amount, second processing for curing an imprint material in a state where the imprint material and the pattern region are in contact with each other and where a second deformation amount is given to the mold by the deforming mechanism to reduce an overlay error between each shot region and the pattern region. A magnitude relation between a driving force of the deforming mechanism required to set a deformation amount of the mold to the first deformation amount and a driving force of the deforming mechanism required to set the deformation amount of the mold to the second deformation amount varies depending on a magnitude of the driving force of the deforming mechanism for setting the deformation amount to the second deformation amount.
Semiconductor device
A semiconductor device is made by: forming an ohmic electrode including Al on a semiconductor substrate; forming a SiN film covering the ohmic electrode; forming a first photoresist on the SiN film, the first photoresist having an opening pattern overlapping the ohmic electrode; performing ultraviolet curing of the first photoresist; forming an opening in the SiN film exposed through the opening pattern and causing a surface of the ohmic electrode to be exposed inside the opening; forming a barrier metal layer on the first photoresist and on the ohmic electrode exposed through the opening; forming a second photoresist in the opening pattern; performing a heat treatment on the second photoresist and covering the barrier metal layer overlapping the opening with the second photoresist; and etching the barrier metal layer using the second photoresist.