Embodiments of the present disclosure generally relate to processes for forming silicon- and boron-containing films for use in, e.g., spacer-defined patterning applications. In an embodiment, a spacer-defined patterning process is provided. The process includes disposing a substrate in a processing volume of a processing chamber, the substrate having patterned features formed thereon, and flowing a first process gas into the processing volume, the first process gas comprising a silicon-containing species, the silicon-containing species having a higher molecular weight than SiH.sub.4. The process further includes flowing a second process gas into the processing volume, the second process gas comprising a boron-containing species, and depositing, under deposition conditions, a conformal film on the patterned features, the conformal film comprising silicon and boron.

A self-assembled nanostructure comprises first domains and second domains. The first domains comprise a first block of a block copolymer material and an activatable catalyst. The second domains comprise a second block and substantially without the activatable catalyst. The activatable catalyst is capable of generating catalyst upon application of activation energy, and the generated catalyst is capable of reacting with a metal oxide precursor to provide a metal oxide. A semiconductor structure comprises such self-assembled nanostructure on a substrate.

Method for producing coating composition applied to patterned resist film in lithography process for solvent development to reverse pattern. The method including: step obtaining hydrolysis condensation product by hydrolyzing and condensing hydrolyzable silane in non-alcoholic hydrophilic solvent; step of solvent replacement wherein non-alcoholic hydrophilic solvent replaced with hydrophobic solvent for hydrolysis condensation product. Method for producing semiconductor device, including: step of applying resist composition to substrate and forming resist film; step of exposing and developing formed resist film; step applying composition obtained by above production method to patterned resist film obtained during or after development in step, forming coating film between patterns; step of removing patterned resist film by etching and reversing patterns. Production method that exposure is performed using ArF laser (with wavelength of 193 nm) or EUV (with wavelength of 13.5 nm). Production method that development is negative development with organic solvent.

A method includes forming a first and a second contact opening to reveal a first and a second source/drain region, respectively, forming a mask layer having a first and a second portion in the first and the second contact openings, respectively, forming a first and a second sacrificial ILD in the first and the second contact openings, respectively, removing the first sacrificial ILD from the first contact opening, filling a filler in the first contact opening, and etching the second sacrificial ILD. The filler protects the first portion of the mask layer from being etched. An ILD is formed in the second contact opening and on the second portion of the mask layer. The filler and the first portion of the mask layer are removed using a wet etch to reveal the first contact opening. A contact plug is formed in the first contact opening.

Provided is a method of forming a trench gate MOSFET. A hard mask layer is formed on a substrate. The substrate is partially removed by using the hard mask layer as a mask, so as to form a trench in the substrate. A first insulating layer and a first conductive layer are formed in the lower portion of the trench. A sacrificial layer is formed on the side surface of the upper portion of the trench, and the sacrificial layer is connected to the hard mask layer. An interlayer insulating layer is formed on the first conductive layer by a thermal oxidation process when the sacrificial layer and the hard mask layer are present. A second insulating layer and a second conductive layer are formed in the upper portion of the trench. A trench gate MOSFET is further provided.

A method of forming a semiconductor device structure is provided. The method includes forming a resist structure over a substrate. The resist structure includes an anti-reflective coating (ARC) layer and a photoresist layer over the ARC layer. The method further includes patterning the photoresist layer to form a trench therein. The method further includes performing a hydrogen plasma treatment to the patterned photoresist layer. The hydrogen plasma treatment is configured to smooth sidewalls of the trench without etching the ARC layer. The method further includes patterning the ARC layer using the patterned photoresist layer as a etch mask.

A method for fabricating a semiconductor device includes forming a first line pattern within sacrificial mandrel material disposed on at least one hard mask layer disposed on a substrate. The first line pattern has a pitch defined by a target line width and a minimum width of space between lines. The method further includes forming, within the first line pattern, a first spacer having a width corresponding to the minimum width of space between lines to minimize pinch points and a first gap having the target line width, and forming a first plug within the first gap corresponding to a first location above the at least one hard mask layer to block pattern transfer into the at least one hard mask layer.

Methods of forming graphene hard mask films are disclosed. Some methods are advantageously performed at lower temperatures. The substrate is exposed to an aromatic precursor to form the graphene hard mask film. The substrate comprises one or more of titanium nitride (TiN), tantalum nitride (TaN), silicon (Si), cobalt (Co), titanium (Ti), silicon dioxide (SiO.sub.2), copper (Cu), and low-k dielectric materials.

Methods of fabricating a three-dimensional semiconductor memory device are provided. A method may include forming a mold structure on a substrate including channel regions and a non-channel region between the channel regions, and forming, on the mold structure, a multilayered mask layer including a first mask layer, an etch stop layer, and a second mask layer that are sequentially stacked. The multilayered mask layer may include mask holes exposing the mold structure in the channel regions, dummy mask holes exposing the first mask layer in the non-channel region, and buffer spacers covering sidewalls of the second mask layer exposed by the mask holes and the dummy mask holes. The method may include etching the mold structure using the multilayered mask layer as an etch mask to form channel holes in the channel regions.

Embodiments of the present disclosure provide methods and apparatus for forming a desired material layer on a substrate between, during, prior to or after a patterning process. In one embodiment, a method for forming a material layer on a substrate includes pulsing a first gas precursor onto a surface of a substrate, attaching a first element from the first gas precursor onto the surface of the substrate, maintaining a substrate temperature less than about 110 degrees Celsius, pulsing a second gas precursor onto the surface of the substrate, and attaching a second element from the second gas precursor to the first element on the surface of the substrate.