A system is disclosed for measuring an impedance of a plasma processing chamber. The system includes a radiofrequency signal generator configured to output a radiofrequency signal based on a frequency setpoint and provide an indication of an actual frequency of the radiofrequency signal, where the actual frequency can be different than the frequency setpoint. The system includes an impedance control module including at least one variable impedance control device. A difference between the actual frequency of the radiofrequency signal as output by the radiofrequency signal generator and the frequency setpoint is partially dependent upon a setting of the at least one variable impedance control device and is partially dependent upon the impedance of the plasma processing chamber. The system includes a connector configured to connect with a radiofrequency signal supply line of the plasma processing chamber. The impedance control module is connected between the radiofrequency signal generator and the connector.

A method of forming a memory device with a dielectric blocking layer and selective silicidation and the resulting device are provided. Embodiments include forming a memory stack on a substrate; forming a conformal insulating layer over sidewalls and an upper surface of the memory stack and the substrate; forming an interpoly dielectric structure adjacent to each sidewall of the insulating layer; forming a conformal polysilicon silicon layer over the insulating layer and interpoly dielectric structures; forming an optical planarization layer over the polysilicon layer; planarizing the optical planarization and polysilicon layers down to the memory stack; forming a dielectric blocking layer over the memory stack and substrate; forming a patterning stack over the dielectric blocking layer, the patterning stack covering a portion of the memory stack; and removing the dielectric blocking, optical planarization, and polysilicon layers on opposite sides of the patterning stack.

The present invention for imaging sensor rejuvenation may include a rejuvenation illumination system configured to selectably illuminate a portion of an imaging sensor of an imaging system with illumination suitable for at least partially rejuvenating the imaging sensor degraded by exposure to at least one of extreme ultraviolet light or deep ultraviolet light; and a controller communicatively coupled to the rejuvenation illumination system and configured to direct the rejuvenation illumination system to illuminate the imaging sensor for one or more illumination cycles during a non-imaging state of the imaging sensor.

The present invention for imaging sensor rejuvenation may include a rejuvenation illumination system configured to selectably illuminate a portion of an imaging sensor of an imaging system with illumination suitable for at least partially rejuvenating the imaging sensor degraded by exposure to at least one of extreme ultraviolet light or deep ultraviolet light; and a controller communicatively coupled to the rejuvenation illumination system and configured to direct the rejuvenation illumination system to illuminate the imaging sensor for one or more illumination cycles during a non-imaging state of the imaging sensor.

Semiconductor devices and methods of forming a semiconductor device that includes a deep shielding pattern that may improve a reliability and/or a functioning of the device. An example method may include forming a wide band-gap semiconductor layer structure on a substrate, the semiconductor layer structure including a drift region that has a first conductivity type; forming a plurality of gate trenches in an upper portion of the semiconductor layer structure, the gate trenches spaced apart from each other, each gate trench having a bottom surface, a first sidewall, a second sidewall, and an upper opening; forming an obstruction over a portion of each gate trench that partially obscures the upper opening; and implanting dopants having a second conductivity type that is opposite the first conductivity type into the bottom surfaces of the gate trenches, where the dopants implanted into the bottom surface of the gate trenches form deep shielding patterns.

A clean silicon wafer, having a DZ layer free of micro-defects formed in a device active region on the surface of the thermally-processed silicon wafer, an IG layer having a high gettering capability formed in a bulk layer, and little heavy metal contamination on the wafer surface is manufactured. A method for manufacturing a silicon wafer for performing the rapid thermal process for a silicon wafer in a furnace, the method performs the rapid thermal process with a thermal budget of 53% or more and 65% or less, in terms of a thermal budget with temperature and time, when a condition where a thermal process at a highest temperature of 1350? C. is maintained for a predetermined longest holding time is taken as 100% of the thermal budget.

A semiconductor device is provided in which a semiconductor substrate can be prevented from being broken while elements can be prevented from being destroyed by a snap-back phenomenon. After an MOS gate structure is formed in a front surface of an FZ wafer, a rear surface of the FZ wafer is ground. Then, the ground surface is irradiated with protons and irradiated with two kinds of laser beams different in wavelength simultaneously to thereby form an N.sup.+ first buffer layer and an N second buffer layer. Then, a P+ collector layer and a collector electrode are formed on the proton-irradiated surface. The distance from a position where the net doping concentration of the N.sup.+ first buffer layer is locally maximized to the interface between the P+ collector layer and the N second buffer layer is set to be in a range of 5 m to 30 m, both inclusively.

A method for manufacturing a silicon wafer having a denuded zone in a surface layer by performing a heat treatment to a silicon wafer, including: a step A, performing a first rapid heat treatment of 0.01 msec or more and 100 msec or less to an upper surface layer alone of the silicon wafer to be treated at 1300 C. or more and a silicon melting point or less by using a first heat source which heats the silicon wafer to be treated from above; and a step B, holding the silicon wafer to be treated at 1100 C. or more and less than 1300 C. for one second or more and 100 seconds or less by a second rapid heat treatment using a second heat source which heats the silicon wafer to be heated, and decreasing the temperature at a falling rate of 30 C./sec or more and 150 C./sec or less.

Porogen accumulation in a UV-cure chamber is reduced by removing outgassed porogen through a heated outlet while purge gas is flowed across a window through which a wafer is exposed to UV light. A purge ring having specific major and minor exhaust to inlet area ratios may be partially made of flame polished quartz to improve flow dynamics. The reduction in porogen accumulation allows more wafers to be processed between chamber cleans, thus improving throughput and cost.

Porogen accumulation in a UV-cure chamber is reduced by removing outgassed porogen through a heated outlet while purge gas is flowed across a window through which a wafer is exposed to UV light. A purge ring having specific major and minor exhaust to inlet area ratios may be partially made of flame polished quartz to improve flow dynamics. The reduction in porogen accumulation allows more wafers to be processed between chamber cleans, thus improving throughput and cost.