An epitaxial wafer that includes a silicon wafer and an epitaxial layer on the silicon wafer. The silicon wafer contains hydrogen that has a concentration profile including a first peak and a second peak. A hydrogen peak concentration of the first peak and a hydrogen peak concentration of the second peak are each not less than 1×10.sup.17 atoms/cm.sup.3.

A method of increasing the resistivity of a silicon carbide wafer includes providing a silicon carbide wafer with a first resistivity, and applying a microwave to treat the silicon carbide wafer. The treated silicon carbide wafer has a second resistivity. The second resistivity is higher than the first resistivity. The microwave treated silicon carbide wafer can be applied in a high-frequency device.

A graphene compound made from the method of preparing graphene flakes or chemical vapor deposition grown graphene films on a SiO.sub.2/Si substrate; exposing the graphene flakes or the chemical vapor deposition grown graphene film to hydrogen plasma; performing hydrogenation of the graphene; wherein the hydrogenated graphene has a majority carrier type; creating a bandgap from the hydrogenation of the graphene; applying an electric field to the hydrogenated graphene; and tuning the bandgap.

To reduce warpage in at least one area of a wafer, a stress/warpage management layer (810) is formed to over-balance and change the direction of the existing warpage. For example, if the middle of the area was bulging up relative to the area's boundary, the middle of the area may become bulging downward, or vice versa. Then the stress/warpage management layer is processed to reduce the over-balancing. For example, the stress/management layer can be debonded from the wafer at selected locations, or recesses can be formed in the layer, or phase changes can be induced in the layer. In other embodiments, this layer is tantalum-aluminum that may or may not over-balance the warpage; this layer is believed to reduce warpage due to crystal-phase-dependent stresses which dynamically adjust to temperature changes so as to reduce the warpage (possibly keeping the wafer flat through thermal cycling). Other features are also provided.

A method includes forming a first high-k dielectric layer over a first semiconductor region, forming a second high-k dielectric layer over a second semiconductor region, forming a first metal layer comprising a first portion over the first high-k dielectric layer and a second portion over the second high-k dielectric layer, forming an etching mask over the second portion of the first metal layer, and etching the first portion of the first metal layer. The etching mask protects the second portion of the first metal layer. The etching mask is ashed using meta stable plasma. A second metal layer is then formed over the first high-k dielectric layer.

A method includes forming a first high-k dielectric layer over a first semiconductor region, forming a second high-k dielectric layer over a second semiconductor region, forming a first metal layer comprising a first portion over the first high-k dielectric layer and a second portion over the second high-k dielectric layer, forming an etching mask over the second portion of the first metal layer, and etching the first portion of the first metal layer. The etching mask protects the second portion of the first metal layer. The etching mask is ashed using meta stable plasma. A second metal layer is then formed over the first high-k dielectric layer.

A method for manufacturing semiconductor structure is disclosed. The method includes: providing a semiconductor substrate; hydrogenizing a surface of the semiconductor substrate; supplying a precursor to the surface of the semiconductor substrate; and supplying a reactant to the surface of the semiconductor substrate. An associated method for performing an atomic layer deposition (ALD) upon a semiconductor substrate and an associated atomic layer deposition (ALD) method are also disclosed.

A method of hydrogenation of a silicon photovoltaic junction device is provided, the silicon photovoltaic junction device comprising p-type silicon semiconductor material and n-type silicon semiconductor material forming at least one p-n junction. The method comprises: i) ensuring that any silicon surface phosphorus diffused layers through which hydrogen must diffuse have peak doping concentrations of 1×10.sup.20 atoms/cm.sup.3 or less and silicon surface boron diffused layers through which hydrogen must diffuse have peak doping concentrations of 1×10.sup.19 atoms/cm.sup.3 or less; ii) Providing one or more hydrogen sources accessible by each surface of the device; and iii) Heating the device, or a local region of the device to at least 40° C. while simultaneously illuminating at least some and/or advantageously all of the device with at least one light source whereby the cumulative power of all the incident photons with sufficient energy to generate electron hole pairs within the silicon (in other words photons with energy levels above the bandgap of silicon of 1.12 eV) is at least 20 mW/cm.sup.2.

A method for producing an electronic component having an electromagnetic shield includes: sticking a temporary protective material to a body to be processed having irregularities on a surface thereof; curing the temporary protective material by light irradiation; singularizing the body to be processed and the temporary protective material; forming a metal film at a part of the singularized body where the temporary protective material is not stuck; and detaching the singularized body having the metal film formed thereon from the temporary protective material. The temporary protective material is formed from a resin composition having a shear viscosity at 35° C. of 5000 to 30000 Pa.Math.s before photocuring and having an elastic modulus at 25° C. of 100 MPa or less and an elongation percentage of 35% or more in a tensile test, after photocuring by light irradiation with an exposure amount of 500 mJ/cm.sup.2 or greater.

A method and structure is provided in which germanium or a germanium tin alloy can be used as a channel material in either planar or non-planar architectures, with a functional gate structure formed utilizing either a gate first or gate last process. After formation of the functional gate structure, and contact openings within a middle-of-the-line (MOL) dielectric material, a hydrogenated silicon layer is formed that includes hydrogenated crystalline silicon regions disposed over the germanium or a germanium tin alloy, and hydrogenated amorphous silicon regions disposed over dielectric material. The hydrogenated amorphous silicon regions can be removed selective to the hydrogenated crystalline silicon regions, and thereafter a contact structure is formed on the hydrogenated crystalline silicon regions.