H01L21/30

Embedded-type transparent electrode substrate and method for manufacturing same

A method of manufacturing a transparent electrode substrate according to an exemplary embodiment includes: a) forming a structure including a transparent base, a bonding layer on a surface of the transparent base, and a metal foil on a surface of the bonding layer opposite the transparent base; b) forming a metal foil pattern by patterning the metal foil; c) heat-treating the structure resulting from b) at a temperature of 70° C. to 100° C.; and d) completely curing the bonding layer. Also, a transparent electrode substrate is disclosed.

Apparatus and systems for substrate processing for lowering contact resistance

Methods, apparatuses, and systems for substrate processing for lowering contact resistance in at least contact pads of a semiconductor device are provided herein. In some embodiments, a method of substrate processing for lowering contact resistance of contact pads includes: circulating a cooling fluid in at least one channel of a pedestal; and exposing a backside of the substrate located on the pedestal to a cooling gas to cool a substrate located on the pedestal to a temperature of less than 70 degrees Celsius. In some embodiments in accordance with the present principles, the method can further include distributing a hydrogen gas or hydrogen gas combination over the substrate.

Substrate processing apparatus, substrate processing method and storage medium storing substrate processing program

A substrate entire region treatment process of discharging a processing fluid of a temperature different from a surface temperature of a substrate 3 from a first nozzle 24 toward the substrate is performed while moving the first nozzle toward an outer side from an entire region treatment start position P2 located at a central portion to an entire region treatment end position P5 located at a peripheral portion. Then, after moving the first nozzle toward an inner side to a peripheral region treatment start position P6 located at an outer position than the entire region treatment start position P2, a substrate peripheral region treatment process of discharging the processing fluid from the first nozzle toward the substrate is performed while moving the first nozzle toward the outer side from the peripheral region treatment start position P6 to a peripheral region treatment stop position P7 located at a peripheral portion.

HYDROGENATION ANNEALING METHOD USING MICROWAVE
20170294316 · 2017-10-12 · ·

Provided is a hydrogenation annealing method using a microwave, which performs hydrogenation annealing at a low temperature and with low power in a manufacturing process of a thin film transistor (TFT) for a display device. The hydrogenation annealing method is constituted by a loading step of loading a device requiring hydrogenation annealing into a chamber and an annealing step of irradiating a microwave having a frequency in an industrial scientific medical (ISM) band into the chamber into which the device is loaded. As hydrogenation annealing is performed at a low temperature by using the microwave for an oxide semiconductor TFT or LTPS having very large electron mobility, high integrated energy is transmitted to the device by the microwave, thereby implementing recoupling of hydrogen atoms which have been performed only at a high temperature, even at a low temperature.

Method for correcting wafer bow from overlay
09824894 · 2017-11-21 · ·

Described herein are methods for flattening a substrate, such as a semiconductor wafer, to reduce bowing in such substrates. Methods include treating or bombarding a backside surface of a substrate with particles of varying doses, densities, and spatial locations. Particle bombardment and selection is such that the substrate becomes more planar by selectively increasing or decreasing z-height points to reduce overall deflection. One or more tensile or compressive films can be added to the backside surface to be selectively relaxed at specific point locations. Such methods can correct bowing in substrates resulting from various fabrication processes such as thermal annealing.

Display device including pixel comprising first transistor second transistor and light-emitting element

An active matrix display device having a pixel structure in which pixel electrodes, gate wirings and source wirings are suitably arranged in the pixel portions to realize a high numerical aperture without increasing the number of masks or the number of steps. The device comprises a gate electrode and a source wiring on an insulating surface, a first insulating layer on the gate electrode and on the source wiring, a semiconductor layer on the first insulating film, a second insulating layer on the semiconductor film, a gate wiring connected to the gate electrode on the second insulating layer, a connection electrode for connecting the source wiring and the semiconductor layer together, and a pixel electrode connected to the semiconductor layer.

Plasma processing method and plasma processing apparatus

Disclosed is a plasma processing method including: growing a polycrystalline silicon layer on a processing target base body; and exposing the polycrystalline silicon layer to hydrogen radicals by supplying a processing gas containing hydrogen into a processing container that accommodates the processing target base body including the polycrystalline silicon layer grown thereon and radiating microwaves within the processing container to generate the hydrogen radicals.

EXTREME ULTRAVIOLET LIGHT GENERATING APPARATUS

A beam adjusting apparatus of an extreme ultraviolet light generating apparatus may include: a first pair of mirrors constituted by a first concave mirror and a first convex mirror, provided along the optical path of the pulsed laser beam; a second pair of mirrors constituted by a second concave mirror and a second convex mirror, which are arranged in an order reversed from the order of arrangement of the first concave mirror and the first convex mirror, provided along the optical path of the pulsed laser beam downstream from the first pair of mirrors; and a moving apparatus configured to simultaneously increase or simultaneously decrease the distance between the first concave mirror and the first convex mirror and the distance between the second concave mirror and the second convex mirror.

EXTREME ULTRAVIOLET LIGHT GENERATING APPARATUS

A beam adjusting apparatus of an extreme ultraviolet light generating apparatus may include: a first pair of mirrors constituted by a first concave mirror and a first convex mirror, provided along the optical path of the pulsed laser beam; a second pair of mirrors constituted by a second concave mirror and a second convex mirror, which are arranged in an order reversed from the order of arrangement of the first concave mirror and the first convex mirror, provided along the optical path of the pulsed laser beam downstream from the first pair of mirrors; and a moving apparatus configured to simultaneously increase or simultaneously decrease the distance between the first concave mirror and the first convex mirror and the distance between the second concave mirror and the second convex mirror.

Hybrid bonding systems and methods for semiconductor wafers

Hybrid bonding systems and methods for semiconductor wafers are disclosed. In one embodiment, a hybrid bonding system for semiconductor wafers includes a chamber and a plurality of sub-chambers disposed within the chamber. A robotics handler is disposed within the chamber that is adapted to move a plurality of semiconductor wafers within the chamber between the plurality of sub-chambers. The plurality of sub-chambers includes a first sub-chamber adapted to remove a protection layer from the plurality of semiconductor wafers, and a second sub-chamber adapted to activate top surfaces of the plurality of semiconductor wafers prior to hybrid bonding the plurality of semiconductor wafers together. The plurality of sub-chambers also includes a third sub-chamber adapted to align the plurality of semiconductor wafers and hybrid bond the plurality of semiconductor wafers together.