The production apparatus includes a shower head electrode, a susceptor for supporting a growth substrate, a first gas supply pipe, and a second gas supply pipe. The first gas supply pipe has at least one first gas exhaust outlet and supplies an organometallic gas containing Group III metal as a first gas, and the second gas supply pipe supplies a gas containing nitrogen gas as the second gas. The distance between the shower head electrode and the susceptor is greater than the distance between the first gas exhaust outlet of the first gas supply pipe and the susceptor.

A method of producing a heterogeneous photonic integrated circuit includes integrating at least one III-V hybrid device on a source substrate having at least a top silicon layer, and transferring by transfer-printing or by flip-chip bonding the III-V hybrid device and at least part of the top silicon layer of the source substrate to a semiconductor-on-insulator or dielectric-on-insulator host substrate.

A method for manufacturing a bonded wafer, includes: ion-implanting a gas ion such as a hydrogen ion from a surface of a bond wafer, thereby forming an ion-implanted layer; bonding the bond wafer and a base wafer; producing a bonded wafer having a thin-film on the base wafer by delaminating the bond wafer along the ion-implanted layer; and performing an RTA treatment on the bonded wafer in a hydrogen gas-containing atmosphere; wherein a protective film is formed onto the surface of the thin-film in a heat treatment furnace in the course of temperature-falling from the maximum temperature of the RTA treatment before the bonded wafer is taken out from the heat treatment furnace; and then the bonded wafer with the protective film being formed thereon is taken out from the heat treatment furnace, and is then cleaned with a cleaning liquid which can etch the protective film and the thin-film.

An imaging system may include an image sensor that may be a backside illuminated (BSI) image sensor. The BSI sensor may be bonded to an inactive silicon substrate or bonded to an active silicon substrate like a digital signal processor (DSP). Through-oxide vias (TOVs) may be formed in the image sensor die. A bond pad region may be formed on a light shielding layer to facilitate coupling the light shield to a ground source or other power sources. Color filter housing structures may be formed over active image sensor pixels on the image sensor die. In-pixel grid structures may be integrated with the color filter housing structures to help reduce crosstalk. The light shielding layer may also be formed over reference image sensor pixels on the image sensor die. The TOVs, the in-pixel grid structures, and the light shielding structures may be formed simultaneously.

Disclosed herein is a laser processing apparatus including a condenser having a function of spherical aberration. Since the condenser has a function of spherical aberration, the focal point of a laser beam to be focused by the condenser and applied to a wafer can be continuously changed in position along the thickness of the wafer. Accordingly, a uniform shield tunnel composed of a fine hole and an amorphous region surrounding the fine hole can be formed so as to extend from, the front side of the wafer to the back side thereof, by one shot of the laser beam.

Disclosed herein is a laser processing apparatus including a condenser having a function of spherical aberration. Since the condenser has a function of spherical aberration, the focal point of a laser beam to be focused by the condenser and applied to a wafer can be continuously changed in position along the thickness of the wafer. Accordingly, a uniform shield tunnel composed of a fine hole and an amorphous region surrounding the fine hole can be formed so as to extend from, the front side of the wafer to the back side thereof, by one shot of the laser beam.

A movable wafer probe may include: an immersion hood including a top body portion and a bottom foot portion, the top body portion having first inner sidewalls surrounding a top opening, the bottom foot portion having second inner sidewalls surrounding a bottom opening; a transducer disposed above the bottom opening and within the top opening, the transducer spaced apart from the first inner sidewalls of the top body portion by a first spacing, the first spacing forming a fluid exhaust port; and a fluid input port extending through the transducer, a bottom end of the fluid input port opening to the bottom opening.

A graphene nanomesh based charge sensor and method for producing a graphene nanomesh based charge sensor. A graphene nanomesh based charge sensor includes a graphene nanomesh with a patterned array of multiple holes created by generating multiple holes in graphene in a periodic way, wherein: an edge of each of the multiple holes of the graphene nanomesh is passivated; and the passivated edge of each of the multiple holes of the graphene nanomesh is functionalized with a chemical compound that facilitates chemical binding of a receptor of a target molecule to the edge of one or more of the multiple holes, allowing the target molecule to bind to the receptor, causing a charge to be transferred to the graphene nanomesh to produce a graphene nanomesh based charge sensor for the target molecule.

A technique disclosed herein relates to a manufacturing method for a semiconductor substrate having the bonded interface with high bonding strength without forming an oxide layer at the bonded interface also for the substrate having surface that is hardly planarized. The manufacturing method for the semiconductor substrate may include an amorphous layer formation process in which a first amorphous layer is formed by modifying a surface of a support substrate and a second amorphous layer is formed by modifying a surface of a single-crystalline layer of a semiconductor. The manufacturing method may include a contact process in which the first amorphous layer and the second amorphous layer are contacted with each other. The manufacturing method may include a heat treatment process in which the support substrate and single-crystalline layer are heat-treated with the first amorphous layer and the second amorphous layer being in contact with each other.

This invention application provides a method for manufacturing a SOI substrate, and the method comprising: providing a first semiconductor substrate; growing a first insulating layer on a top surface of the first semiconductor substrate for forming a first wafer; irradiating the first semiconductor substrate via a ion beam for forming a deuterium and helium co-doping layer to a pre-determined depth from a top surface of the first insulating layer; growing a second insulating layer on a top surface of the second semiconductor substrate for form a second wafer; bonding the first wafer with the second wafer; annealing the first wafer and second wafer; separating a part of the first wafer from the second wafer; and forming a deuterium and helium co-doping semiconductor layer on the second wafer.