Patent classifications
H01L21/67282
SECURE ONE-TIME WAFER IDENTIFICATION IN SPLIT MANUFACTURING
A method of wafer verification for split manufacturing is provided. The method includes capturing images of one or more different wafer features during manufacturing using a fiducial marker. The method further includes comparing the images from one stage to a next stage for at least two stages of manufacturing to verify a wafer identification based on a matching of the one of more different wafer features from the one stage to the next stage.
Method of arranging a plurality of semiconductor structural elements on a carrier and carrier comprising a plurality of semiconductor structural elements
A method of arranging a plurality of semiconductor structural elements on a carrier includes arranging at least some of the semiconductor structural elements in multiple groups G and at least one semiconductor structural element of a group G has a property E that determines the position of the respective group G of semiconductor structural elements on the carrier.
Carbide, Nitride And Silicide Enhancers For Laser Absorption
A compounded polymer material that can be laser marked is provided. The compounded polymer material includes an enhancer of nitrides, carbides, silicides, or combinations thereof. Upon forming the compounded polymer material into an article and exposing it to laser radiation, the irradiated portion of the compounded polymer material absorbs the laser radiation, increases in temperature, and forms a mark in the article. A lightness value difference (L) between the mark and the non-irradiated portion of the article has an absolute value of at least 5, and the lightness value difference between the mark and the non-irradiated portion is greater than if the polymer material did not include the enhancer.
INSPECTION SYSTEM AND INSPECTION METHOD
An inspection system includes a laser light source, an optical system for laser marking that irradiates a semiconductor device with laser light from a metal layer side, a control unit that controls the laser light source to control laser marking, a two-dimensional camera that detects light from the semiconductor device on a substrate side and outputs an optical reflection image, and an analysis unit that generates a pattern image of the semiconductor device, and the control unit controls the laser light source so that laser marking is performed until a mark image appears in a pattern image.
PATTERN FORMING APPARATUS AND MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE
A pattern forming apparatus according to an embodiment includes: a pre-alignment unit that performs pre-alignment for a substrate; a transfer unit that transfers the substrate into the pre-alignment unit; a placing table on which the substrate transferred into the pre-alignment unit is placed; a position detecting unit provided at a position included in the placing table and overlapping with an edge of the substrate, and adapted to detect a position of the edge of the substrate; and a control unit that calculates a positional displacement amount of the substrate from the position of the edge of the substrate detected by the position detecting unit, and controls the placing table on the basis of the positional displacement amount of the substrate to correct the position of the substrate.
PROCESSING METHOD FOR REMOVING FILM AND APPARATUS FOR REMOVING FILM
Embodiments of the present disclosure provide a processing method for removing film and apparatus for removing film. The apparatus for removing film includes an optical component and a processor, in which the optical component includes: a laser generator configured to generate a laser beam; a first scanning galvanometer configured to reflect the laser beam; and a second scanning galvanometer configured to reflect the laser beam reflected by the first scanning galvanometer. The processor is configured to control the laser generator to generate a laser beam, and control the first scanning galvanometer and the second scanning galvanometer to deflect, thereby performing the film removal process on the target object.
INTEGRATED CIRCUIT SECURITY
Verifying a semiconductor product is disclosed. An image of a self-assembly (SA) pattern on a substrate from a scanner is received. The SA pattern has been initially created using a block copolymer (BCP) which has been annealed on the substrate. Data from the SA pattern is stored in a computer system. The SA pattern data is associated with the semiconductor product. The SA pattern is an information carrying security mark having a set of features with corresponding locations within the information carrying security mark which uniquely identify the semiconductor product.
Inspection system and inspection method
An inspection system includes a laser light source, an optical system for laser marking that irradiates a semiconductor device with laser light from a metal layer side, a control unit that controls the laser light source to control laser marking, a two-dimensional camera that detects light from the semiconductor device on a substrate side and outputs an optical reflection image, and an analysis unit that generates a pattern image of the semiconductor device, and the control unit controls the laser light source so that laser marking is performed until a mark image appears in a pattern image.
Integrated circuit security
A semiconductor product includes a substrate having a self-assembly (SA) pattern. An initial SA pattern is created using a block copolymer (BCP) which has been annealed on the substrate. The initial SA pattern and/or an enlarged SA pattern derived from the initial SA pattern is incorporated into the semiconductor product. The SA pattern is an information carrying security mark having a set of features with corresponding locations within the information carrying security mark which uniquely identify the semiconductor product. In other embodiments of the invention a method and system for creating the semiconductor product are described.
Solderable and wire bondable part marking
A technique for marking semiconductor devices with an identifiable mark or alphanumeric text yields a high-contrast, easily distinguishable mark on an electrical terminal of the device without impacting the device's breakdown voltage capability and without compromising the solderability and wire bondability of the terminal. This approach deposits the mark on the terminal as a patterned layer of palladium, which offers good contrast with the base metal of the terminal and maintains the solderability and bondability of the terminal.