A segmented detector device with backside illumination. The detector is able to collect and differentiate between secondary electrons and backscatter electrons. The detector includes a through-hole for passage of a primary electron beam. After hitting a sample, the reflected secondary and backscatter electrons are collected via a vertical structure having a P+/P−/N+ or an N+/N−/P+ composition for full depletion through the thickness of the device. The active area of the device is segmented using field isolation insulators located on the front side of the device.

A method for in situ protection of a surface (7a) of an aluminum layer (7) of a VUV radiation reflecting coating (6) of an optical element (4), arranged in an interior of an optical arrangement, against the growth of an aluminum oxide layer (8), including carrying out an atomic layer etching process for layer-by-layer removal of the aluminum oxide layer from the surface. The etching process includes a surface modification step and a material detachment step. At least one boron halide is supplied as a surface modifying reactant to the interior in pulsed fashion during the surface modification step. A plasma is generated at a surface (8a) of the aluminum oxide layer, at least during the material detachment step. The atomic layer etching process is performed until the aluminum oxide layer reaches a given thickness (D), or the aluminum oxide layer is kept below that thickness (D) by the process.

The present disclosure relates to dual beam device and three-dimensional circuit pattern inspection techniques by cross sectioning of inspection volumes with large depth extension exceeding 1 μm below the surface of a semiconductor wafer, as well as methods, computer program products and apparatuses for generating 3D volume image data of a deep inspection volume inside a wafer without removal of a sample from the wafer. The disclosure further relates to 3D volume image generation and cross section image alignment methods utilizing a dual beam device for three-dimensional circuit pattern inspection.

A method of manufacturing a packaged semiconductor device is provided. The method includes placing a plurality of semiconductor die on a carrier substrate. The plurality of semiconductor die and an exposed portion of the carrier substrate are encapsulated with an encapsulant. A cooling fixture includes a plurality of nozzles and is placed over the encapsulant. The encapsulant is cooled by way of air exiting the plurality of nozzles. A property of air exiting a first nozzle of the plurality of nozzles is different from that of a second nozzle of the plurality of nozzles.

This application relates to a method of processing microelectronic components comprising measuring parameter values of at least one of a nature and a degree of warpage of singulated microelectronic components in an unconstrained state and sorting the singulated microelectronic components responsive to the measured parameter values of at least one of the nature and degree of warpage. The sorted dice may be used in assemblies to minimize bond line height variances and resulting open circuits between components. Systems for implementing the methods are also disclosed.

A FinFET structure with a gate structure having two notch features therein and a method of forming the same is disclosed. The FinFET notch features ensure that sufficient spacing is provided between the gate structure and source/drain regions of the FinFET to avoid inadvertent shorting of the gate structure to the source/drain regions. Gate structures of different sizes (e.g., different gate widths) and of different pattern densities can be provided on a same substrate and avoid inadvertent of shorting the gate to the source/drain regions through application of the notched features.

According to one embodiment, a processing information management system includes: an abnormality analyzer configured to generate abnormality occurrence data of a target wafer based on processing location information, the processing location information collected based on a first sensor outputting a first sensor signal according to a detected processing state, the first sensor provided in a wafer processing apparatus; and an integration system configured to integrate the abnormality occurrence data into wafer map data corresponding to the target wafer.

A method for operating a conveying system is provided. An overhead hoist transport (OHT) vehicle is provided, wherein the OHT vehicle includes a gripping member configured to grip and hold a carrier, and a receiver configured to receive a signal. The signal is transmitted to the receiver of the OHT vehicle. The OHT vehicle is moved toward the carrier, and the carrier is gripped by the gripping member of the OHT vehicle. A lifting force is determined based on a weight of a carrier, a number of workpieces in the carrier, or a vertical distance between the OHT vehicle and the carrier, and the lifting force is applied to the carrier.

A control unit performs a travel stop process for stopping travel of a travel unit in response to an indicator detection unit detecting a stop notice indicator section and then detecting a stop position indicator section. After the travel of the travel unit is stopped as a result of the travel stop process, the control unit performs a transfer process for causing a transfer unit to transfer an article. The control unit performs, instead of the transfer process, anomaly notification processing for providing a notification of an occurrence of an anomaly to a superordinate control unit, after the travel of the travel unit is stopped by the travel stop process, in response to: (i) a travel distance, from a position at which the indicator detection unit has detected the stop notice indicator section, being smaller than a determination distance smaller than a notice distance, and (ii) the indicator detection unit detecting the stop position indicator section.

Wafers that begin as flat surfaces during a semiconductor manufacturing process may become warped or bowed as layers and features are added to an underlying substrate. This warpage may be detected between manufacturing processes by rotating the wafer adjacent to a displacement sensor. The displacement sensor may generate displacement data relative to a baseline measurement to identify areas of the wafer that bow up or down. The displacement data may then be mapped to locations on the wafer relative to an alignment feature. This mapping may then be used to adjust parameters in subsequent semiconductor processes, including adjusting how a carrier head on a polishing process holds or applies pressure to the wafer as it is polished. A model may be trained to provide control signals for a polishing/cleaning process, or to generate metrology data.