H01L21/67294

Substrate storage container management system, load port, and substrate storage container management method

A substrate storage container management system includes a load port, configured to transfer a substrate into and out of one or more substrate storage containers, including an ID reader configured to read one or more entity IDs for the substrate storage containers, and one or more sensors configured to directly or indirectly detect one or more states of the substrate storage containers, an associator configured to associate the entity IDs read by the ID reader with one or more sensor values detected by the sensors; a database in which data associated by the associator is accumulated, and a data processor configured to analyze the data in the database and to output a state of a respective substrate storage container for each of the entity IDs.

Device positioning using sensors

A method for positioning a mobile device relative to a stationary device in a semiconductor manufacturing environment is disclosed. The method includes detecting a target affixed to the stationary device at a target location, wherein the target location corresponds to a location of the target relative to a reference point on the stationary device, determining a first position coordinate offset value based upon detecting the target, and moving the mobile device, using the first position coordinate offset value, relative to train the mobile device to move relative to the stationary device for the stationary device to performing a semiconductor manufacturing operation.

SECURE INSPECTION AND MARKING OF SEMICONDUCTOR WAFERS FOR TRUSTED MANUFACTURING THEREOF
20210134682 · 2021-05-06 ·

A method for securing and verifying semiconductor wafers during fabrication includes receiving a semiconductor wafer after a layer of features has been patterned thereon. At least one security mark is formed at one or more locations embedded within a backside of the semiconductor wafer by implanting an inert species at the one or more locations. At a subsequent point in fabrication and/or after fabrication of the semiconductor wafer has completed the backside of the wafer is inspected for detection of the at least one security mark. If the at least one security mark is not detected at an expected location within the backside of the semiconductor wafer a determination is made that the semiconductor wafer has been compromised.

SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING APPARATUS CONTROL METHOD
20230411189 · 2023-12-21 ·

A substrate processing method includes: a first step of causing, in a state of a substrate holding mechanism not holding a plurality of substrates, a camera to capture an image of the substrate holding mechanism and an image of an interior to generate first image data; a second step of identifying, in a first region indicated by the first image data, a second region being a region in which at least the image of the substrate holding mechanism has been captured; and a third step of comparing a gradient of the first image data distributed in a third region being a region in the first region other than the second region with a threshold for the gradient.

METHOD FOR CONTROLLING CONVEYANCE SYSTEM, CONVEYANCE SYSTEM, AND MANAGEMENT DEVICE
20210057254 · 2021-02-25 ·

A method for controlling a conveyance system includes transmitting, by a specific conveyance vehicle specific transfer location information to a management device, extracting from correspondence information by the management device, specific communication-device address information corresponding to the specific transfer location information received from the specific conveyance vehicle, and transmitting to the specific conveyance vehicle by the management device the specific communication-device address information extracted, and executing by the specific conveyance vehicle using the specific communication-device address information received from the management device communication with a first communication device connected to a first semiconductor manufacturing device to transfer a FOUP between the first semiconductor manufacturing device and the specific conveyance vehicle.

LOAD LOCK FOR A SUBSTRATE CONTAINER AND DEVICE HAVING SUCH A LOAD LOCK
20210082723 · 2021-03-18 ·

A load lock for a substrate container for receiving flat substrates, wherein the load lock has a load chamber for receiving the substrate container that has a bottom, a ceiling, a rear wall, a front wall, a first side wall and a second side wall that connect the rear wall to the front wall, and wherein a carrier unit for receiving the substrate container is arranged in the load chamber. Here, it is provided that the load chamber can be divided into a first part and a second part along a dividing plane to open the load chamber, wherein the dividing plane extends toward the rear wall offset from the front wall through the first side wall, the second side wall, the bottom and the ceiling of the load chamber.

RFID part authentication and tracking of processing components

Embodiments provided herein provide for methods and apparatus for detecting, authenticating, and tracking processing components including consumable components or non-consumable components used on substrate processing systems for electronic device manufacturing, such as semiconductor chip manufacturing. The semiconductor processing systems and/or its processing components herein include a remote communication device, such as a wireless communication apparatus, for example radio frequency identification (RFID) devices or other devices embedded in, disposed in, disposed on, located on, or otherwise coupled to one or more processing components or processing component assemblies and/or integrated within the semiconductor processing system itself. The processing component may include a single component (part) or an assembly of components (parts) that are used within the semiconductor processing tool.

SYSTEMS AND METHODS FOR DIE TRANSFER

In certain embodiments, a system includes: a source lane configured to move a first die container between a load port and a source lane staging area; an inspection sensor configured to produce a sensor result based on a die on the first die container; a pass target lane configured to move a second die container between a pass target lane out port and a pass target lane staging area; a fail target lane configured to move a third die container between a fail target lane out port and a fail target lane staging area; and a conveyor configured to move the die from the first die container at the source lane staging area to either the second die container at the pass target lane staging area or the fail target lane staging area based on the sensor result.

Apparatus and methods for determining wafer characters

Apparatus and methods for determining wafer characters are disclosed. In one example, an apparatus is disclosed. The apparatus includes: a processing tool configured to process a semiconductor wafer; a device configured to read an optical character disposed on the semiconductor wafer while the semiconductor wafer is located at the apparatus for wafer fabrication; and a controller configured to determine whether the optical character matches a predetermined character corresponding to the semiconductor wafer based on the optical character read in real-time at the apparatus.

METHOD AND APPARATUS FOR SUBSTRATE ALIGNMENT
20210082729 · 2021-03-18 ·

A semiconductor wafer transport apparatus having a transport arm and at least one end effector. An optical edge detection sensor is coupled to the transport arm and is configured so as to register and effect edge detection of a wafer supported by the end effector. An illumination source illuminates a surface of the wafer and is disposed with respect to the optical edge detection sensor so that the surface directs reflected surface illumination, from the illumination source, toward the optical edge detection sensor, and optically blanks, at the peripheral edge of the wafer, background reflection light of a background, viewed by the optical edge detection sensor coincident with linear traverse of the wafer supported by the at least one end effector. The peripheral edge of the wafer is defined in relief in image contrast to effect edge detection coincident with traverse of the wafer supported by the end effector.