An electronic package having a miniaturized footprint and a method for manufacturing the same is provided. Due to the arrangement of bottom contacts of the electronic package using a first partial vias, a footprint is obtained that is miniaturized with respect to the known electronic package comprising a same-sized electronic component. The electronic package according to the present disclosure enables packaging multiple electronic components while nevertheless minimally increasing the footprint with respect to conventional electronic packages.

Provided is a method of manufacturing a semiconductor having a double-sided substrate including preparing a first substrate on which a specific pattern is formed to enable electrical connection, preparing at least one semiconductor chip bonded to a metal post, bonding the at least one semiconductor chip to the first substrate, bonding a second substrate to the metal post, forming a package housing by packaging the first substrate and the second substrate to expose a lead frame, and forming terminal leads toward the outside of the package housing. Accordingly, the semiconductor chip and the metal post are previously joined to each other and are respectively bonded to the first substrate and the second substrate so that damage generated while bonding the semiconductor chip may be minimized and electrical properties and reliability of the semiconductor chip may be improved.

A package structure includes a first circuit board, a second circuit board, at least one electronic component, at least one conductive lead, and a molding compound. The first circuit board includes a first circuit layer and a second circuit layer. The second circuit board includes a third circuit layer and a fourth circuit layer. The electronic component is disposed between the first circuit board and the second circuit board. The conductive lead contacts at least one of the second circuit layer and the third circuit layer. The conductive lead has a vertical height, and the vertical height is greater than a vertical distance between the second circuit layer and the third circuit layer. The molding compound covers the first circuit board, the second circuit board, the electronic component, and the conductive lead. The molding compound exposes the first circuit layer and the fourth circuit layer, and the conductive lead extends outside the molding compound.

A power component includes two electric terminals, a component housing, a main component at least partially surrounded by the component housing, connected with the two terminals, and configured to carry a power current flowing between the two electric terminals, and a sensor and emitter unit which is configured to measure a value of a physical quantity (T, V, ΔV) characterizing an operating state of the main component, and to emit an electromagnetic signal, in which the measured value of the physical quantity is encoded. The sensor and emitter unit includes an antenna for emitting the electromagnetic signal which is spaced apart from the main component and arranged in, on and/or at the component housing.

A semiconductor device having a fan-out package structure includes a semiconductor element having a first electrode pad and a second electrode pad on a front surface, a sealing material covering a side surface of the semiconductor element and a redistribution layer covering the front surface of the semiconductor element and a part of the sealing material. The redistribution layer includes an insulation layer, a first redistribution wire and a second redistribution wire. At least a part of the first redistribution layer is disposed above a boundary between the side surface of the semiconductor element and the sealing material. The second redistribution wire is electrically connected to the second electrode pad, and at least has a part that extends to a position outside of a contour of the semiconductor element over the first redistribution wire. The second redistribution wire is electrically independent of the first redistribution wire.

An object of the present invention is to provide a technique capable of reducing a gap between a first semiconductor device and a second semiconductor device that are bonded. At least one of a pair of a first electrode of the first semiconductor device and a second electrode of the second semiconductor device and a pair of a second electrode of the first semiconductor device and a first electrode of the second semiconductor device is electrically connected, and for each of the first semiconductor device and the second semiconductor device, each of a thickness of a portion from a first connected portion to a second connected portion and a thickness of a holding member are equal to or less than a thickness of a first main body portion or a thickness of a second main body portion.

A sheet-shaped member 440 including a resin insulating layer 441 and a metal foil 442 is used. The sheet-shaped member 440 is deformed following warpage or step difference in a second conductor plate 431 and a fourth conductor plate 433, and therefore, the thickness of the resin insulating layer 441 can be set to a constant thickness of, for example, 120 μm capable of securing insulation properties. By plastically deforming a metal-based heat conduction member 450 having a thickness of, for example, 120 μm interposed between the sheet-shaped member 440 and a cooling member 340, the thickness of the metal-based heat conduction member 450 is changed to absorb the warpage or step difference generated in the second conductor plate 431 and the fourth conductor plate 433. This results in remarkable improvement in heat dissipation as compared with a case where the conductor plates are brought into contact with the cooling member 340 via an insulating layer alone.

A semiconductor layer having an opening and a MEMS resonator formed in the opening is disposed between first and second substrates to encapsulate the MEMS resonator. An electrical contact that extends from the opening to an exterior of the MEMS device is formed at least in part within the semiconductor layer and at least in part within the first substrate.

A semiconductor layer having an opening and a MEMS resonator formed in the opening is disposed between first and second substrates to encapsulate the MEMS resonator. An electrical contact that extends from the opening to an exterior of the MEMS device is formed at least in part within the semiconductor layer and at least in part within the first substrate.

The present disclosure relates to a high voltage power electronics module for subsea applications. The power electronics module includes: a baseplate, a power semiconductor chip arranged on the baseplate, and an encapsulation structure arranged on the baseplate and configured to encapsulate the power semiconductor chip, wherein the encapsulation structure is an epoxy having an elastic modulus less in a range of 1 to 20 Giga Pascal, GPa, at room temperature and a coefficient of thermal expansion less than 20 ppm/K.