A pattern for heat transfer material for a thermal transfer interface having a high aspect ratio. Two thermal interface elements (e.g., a die and a cover) meet to form a thermal interface with a high aspect ratio (i.e., the ratio of length to width is above a threshold such as 9:5). The pattern includes two star-shaped patterns aligned side-by-side in the lengthwise (longer dimension) direction. Each star pattern includes spokes emanating from a local central point. The pattern optionally includes a central cross shape that includes a vertical line extending between the two longer edges and a horizontal thickened section in which horizontally aligned spokes are thickened. When pressed between two thermal interface elements, this pattern performs better (e.g., covers more area) than a more traditional pattern, thereby improving heat transfer ability.

Example embodiments relate to electronic packages and electronic devices that include the same. One embodiment includes an electronic package. The electronic package includes a package body. The electronic package also includes a heat-conducting substrate arranged inside the package body and having a bottom surface that is exposed to an outside of the package body. Additionally, the electronic package includes an electronic circuit arranged inside the package body and including a semiconductor die that has a bottom surface with which it is mounted to the heat-conducting substrate and an opposing upper surface. Further, the electronic package includes one or more leads partially extending from outside the package body to inside the package body and over the minimum bounding box, each lead having a first end that is arranged inside the package body. In addition, the electronic package includes one or more bondwires for connecting the first end(s) to the electronic circuit.

A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and a method of manufacturing thereof, that comprises a first semiconductor die, a plurality of adhesive regions spaced apart from each other on the first semiconductor die, and a second semiconductor die adhered to the plurality of adhesive regions.

A housing for an electronic circuit configuration includes a housing seal disposed on an inner surface of the housing, integrally bonded to at least one outer housing wall and made of a liquid silicone elastomer. An electrical connecting element extends from the interior of the housing through an outer housing wall and out of the housing. A space between the outer housing wall and the electrical connecting element is sealed by the housing seal.

A semiconductor package includes a module substrate having opposite top and bottom surfaces, a semiconductor chip provided with bumps and mounted on the top surface of the module substrate via the bumps, and a metal member having a top portion disposed at a level higher than the semiconductor chip with reference to the top surface of the module substrate and including the semiconductor chip in plan view and a side portion extending from the top portion toward the module substrate. The module substrate includes a first metal film disposed on or in at least one of the bottom surface and an internal layer of the module substrate. The first metal film is electrically connected to the bumps and reaches a side surface of the module substrate. The side portion is thermally coupled to the first metal film at the side surface of the module substrate.

A semiconductor package includes a module substrate having opposite top and bottom surfaces, a semiconductor chip provided with bumps and mounted on the top surface of the module substrate via the bumps, and a metal member having a top portion disposed at a level higher than the semiconductor chip with reference to the top surface of the module substrate and including the semiconductor chip in plan view and a side portion extending from the top portion toward the module substrate. The module substrate includes a first metal film disposed on or in at least one of the bottom surface and an internal layer of the module substrate. The first metal film is electrically connected to the bumps and reaches a side surface of the module substrate. The side portion is thermally coupled to the first metal film at the side surface of the module substrate.

There are provided a semiconductor module capable of preventing the adhesion of an epoxy resin to a terminal to which at least one of a high current and a high voltage is supplied and a method for manufacturing a semiconductor module. A semiconductor module includes: a case having an inner wall defining a casting region and a peripheral edge portion arranged outside the inner wall; an intermediate terminal arranged in along side portion of a peripheral edge portion and having a fastening surface to which a cable is fastened; a structure arranged in a long side portion of the inner wall to be adjacent to the long side portion where the intermediate terminal is arranged and higher than the fastening surface; and a sealing section formed of an epoxy resin, having weld lines formed close to the side of the structure on a surface, and cast into a casting region to seal transistors.

There are provided a semiconductor module capable of preventing the adhesion of an epoxy resin to a terminal to which at least one of a high current and a high voltage is supplied and a method for manufacturing a semiconductor module. A semiconductor module includes: a case having an inner wall defining a casting region and a peripheral edge portion arranged outside the inner wall; an intermediate terminal arranged in along side portion of a peripheral edge portion and having a fastening surface to which a cable is fastened; a structure arranged in a long side portion of the inner wall to be adjacent to the long side portion where the intermediate terminal is arranged and higher than the fastening surface; and a sealing section formed of an epoxy resin, having weld lines formed close to the side of the structure on a surface, and cast into a casting region to seal transistors.

Embodiments of the present disclosure include a semiconductor device and methods of forming a semiconductor device. An embodiment is a method of forming a semiconductor device, the method including bonding a die to a top surface of a first substrate, the die being electrically coupled to the first substrate, and forming a support structure on the top surface of the first substrate, the support structure being physically separated from the die with a top surface of the support structure being coplanar with a top surface of the die. The method further includes performing a sawing process on the first substrate, the sawing process sawing through the support structure.

Embodiments of the present disclosure include a semiconductor device and methods of forming a semiconductor device. An embodiment is a method of forming a semiconductor device, the method including bonding a die to a top surface of a first substrate, the die being electrically coupled to the first substrate, and forming a support structure on the top surface of the first substrate, the support structure being physically separated from the die with a top surface of the support structure being coplanar with a top surface of the die. The method further includes performing a sawing process on the first substrate, the sawing process sawing through the support structure.