A package includes a semiconductor carrier, a first die, a second die, a first encapsulant, a second encapsulant, and an electron transmission path. The first die is disposed over the semiconductor carrier. The second die is stacked on the first die. The first encapsulant laterally encapsulates the first die. The second encapsulant laterally encapsulates the second die. The electron transmission path is electrically connected to a ground voltage. A first portion of the electron transmission path is embedded in the semiconductor carrier, a second portion of the electron transmission path is aside the first die and penetrates through the first encapsulant, and a third portion of the electron transmission path is aside the second die and penetrates through the second encapsulant.

A semiconductor device includes: an insulating substrate; a first conductor portion and a second conductor portion that are formed on the insulating substrate; a semiconductor element disposed on the first conductor portion; a first terminal that is connected to a first electrode of the semiconductor element; a second terminal that is connected to the first conductor portion; a connection member electrically connecting a control electrode of the semiconductor element and the second conductor portion to each other; a support member that is disposed at a predetermined distance from the second conductor portion; a pin terminal having that is supported in a state of being inserted through the support member and connected to the second conductor portion; and a sealing resin that seals the insulating substrate, the first conductor portion, the second conductor portion, the semiconductor element, the connection member, and the support member.

A semiconductor module includes a main board and external terminals. A package substrate includes a core insulation layer, a conductive pattern disposed in the core insulation layer and electrically connected with the external terminals, an upper insulation pattern and a lower insulation pattern. At least one semiconductor chip is disposed on an upper surface of the package substrate and is electrically connected with the conductive pattern. A shielding plate is disposed on a molding member and lateral side surfaces of the package substrate and shields electromagnetic interference (EMI) emitted from the semiconductor chip. A shielding fence extends from an edge portion of a lower surface of the lower insulation pattern and directly contacts the upper surface of the main board. The shielding fence surrounds the external terminals and shields EMI emitted from the external terminals. A reinforcing member increases a strength of the shielding fence.

Disclosed are a semiconductor package and a manufacturing method thereof. Semiconductor chips may be disposed on a package substrate with vent holes formed therethrough, and a molding layer including a lower molding portion connected to an upper molding portion may be formed. The package substrate may include a substrate body with a plurality of unit regions, ball lands disposed in the unit regions, and first and second dam patterns that cross the unit regions and extend into edge regions, which is outside of the unit regions.

A semiconductor device includes: plural conductor portions formed on an insulating substrate; a semiconductor element disposed on one of the plural conductor portions on the insulating substrate; a support member that is disposed at a predetermined distance from one of the plural conductor portions on the insulating substrate; a columnar pin terminal that is supported by the support member and is connected to the one of the plural conductor portions on the insulating substrate from which the support member is disposed at the predetermined distance; and a sealing resin that seals the insulating substrate, the plural conductor portions, the semiconductor element, and the support member. The support member has a through-hole having a polygonal shape and penetrating in a plate thickness direction of the support member, and the pin terminal is supported by the support member in a state in which the pin terminal is inserted through the through-hole.

A packaged antenna circuit structure suitable for 5G use includes a shielding layer, an electronic component, conductive pillars, a first insulation layer, a first stacked structure, an antenna structure, and a second stacked structure. The shielding layer defines a groove to receive the electronic component. The conductive pillars on the shielding layer surround the groove. The first insulation layer covers the shielding layer, the electronic component, and the conductive pillars. The first stacked structure is stacked on a side of the first insulation layer and includes a ground line connecting to the conductive pillars. The antenna structure is stacked on a side of the first stacked structure away from the first insulation layer and connected to the electronic component by the first stacked structure. The second stacked structure is stacked on a side of the first insulation layer away from the first stacked structure.

Provided is a semiconductor package having a package housing in an engraved surface form and a method of manufacturing the same, wherein the semiconductor package includes: at least one substrate on which at least one semiconductor chip is installed; at least one terminal lead electrically connected to the substrates; electrical connectors for connecting the semiconductor chips to the substrates or the terminal leads; a package housing covering the semiconductor chips, the electrical connectors, and the at least one substrate; at least one stopper which is formed of a material same as that of the package housing, is higher by a certain height than exposed surfaces of the substrates, is disposed on the exposed surfaces of the substrates, or covers at least a part of the exposed surfaces; and at least one heat sink transmitting heat from the semiconductor chips and radiating heat, wherein the at least a part of the exposed surfaces of the at least one substrate is formed on the upper surface, the lower surface, or the upper and lower surfaces of the package housing and the exposed surfaces of the at least one substrate are joined to the heat sinks by using heat transfer connectors interposed therebetween. Accordingly, the full thickness of the heat transfer connectors may be uniformly maintained.

A semiconductor device module includes a device mounted on the surface of an organic substrate; a heat dissipation block bonded and fixed to the surfaces of the device; and a molded resin sealing the device with at least one surface of the heat dissipation block being exposed. The heat dissipation block includes a first portion and a second portion made of materials different in hardness: the first portion is harder than the second portion, and a gradient in hardness from the first portion on the side exposed from the molded resin to the second portion on the side bonded to the device, to keep a good grinding performance of grinding wheel.

An integrated circuit (IC) assembly and a method for encapsulating of IC are presented. The IC assembly comprises an IC substrate having one or more micro-devices, at least one dielectric matrix element placed on said IC substrate over at least one of its one or more micro-devices; and an encapsulation element applied over said IC substrate and said at least one dielectric matrix element placed thereon to enclose and seal said IC substrate.

A power module (10) and a manufacturing method thereof are disclosed. The power module (10) includes a power assembly (11) and a drive board (12). The power assembly (11) includes a substrate (111), a power chip (112), and a package body (113). The power chip (112) is disposed on a mounting surface (1110) of the substrate (111). The package body (113) packages the power chip (112) on the substrate (111). The drive board (12) is disposed in the package body (113) and is located on a side, of the power chip (112), that backs the mounting surface (1110). The drive board (12) is electrically connected to the power chip (112). In the power module, a parasitic parameter between the drive board (12) and the power assembly (11) can be reduced, thereby improving electrical performance of the power module (10).