A circuit module 2 comprises: a wiring structure 4; at least one electronic component 6a, 6b arranged on the upper surface of the wiring structure 4; an insulating resin layer 8 which is provided on the upper surface of the wiring structure 4 and in which at least one electronic component 6a, 6b is embedded; and a metal layer 10 provided on the upper surface of the insulating resin layer 8. The surface roughness of the portion S1 directly above each electronic component on the upper surface of the insulating resin layer 8 is expressed as R1. The surface roughness of the portion S2 other than the portion directly above all the electronic components on the upper surface of the insulating resin layer 8 is expressed as R2. At least one R1 satisfies the condition: R1>R2.

An electronic device includes a die attach pad with a set of cantilevered first leads for down bond connections, a set of second leads spaced apart from the die attach pad, a semiconductor die mounted to the die attach pad and enclosed by a package structure, a set of first bond wires connected between respective bond pads of the semiconductor die and at least some of the first leads, and a set of second bond wires connected between respective further bond pads of the semiconductor die and at least some of the second leads.

A display apparatus includes: a substrate having a display area and a peripheral area outside the display area; a first insulating layer over both the display area and the peripheral area; a first dam over the peripheral area and spaced apart from the first insulating layer; an electrode power supply line, at least a part of the electrode power supply line being located between the first insulating layer and the first dam; a protection conductive layer over the first insulating layer, the protection conductive layer extending over the electrode power supply line and electrically connected to the electrode power supply line; a pixel electrode over the first insulating layer in the display area; an opposite electrode over the pixel electrode; and a capping layer covering the opposite electrode and extending outside the opposite electrode such that an end of the capping layer is on the first insulating layer.

A method of manufacturing a semiconductor package may include providing a substrate having first and second cutting regions respectively provided along first and second side portions opposite to each other and a mounting region between the first and second cutting regions is provided, disposing at least one semiconductor chip on the mounting region, forming a molding member on the substrate, and removing a dummy curl portion and at least portions of dummy runner portions from the molding member. The molding member may include a sealing portion, the dummy curl portion provided outside the second side portion of the substrate, and the plurality of dummy runner portions on the second cutting region to connect the sealing portion and the dummy curl portion. The substrate may include adhesion reducing pads in the second cutting region, which may contact the dummy runner portions respectively.

A semiconductor device includes a substrate; a semiconductor chip located on the substrate; a sealing resin covering the substrate and the semiconductor chip; and a mottled pattern located at an interface between the sealing resin and at least one of the substrate or the semiconductor chip.

A semiconductor device with redistribution layers formed utilizing dummy substrates is disclosed and may include forming a first redistribution layer on a first dummy substrate, forming a second redistribution layer on a second dummy substrate, electrically connecting a semiconductor die to the first redistribution layer, electrically connecting the first redistribution layer to the second redistribution layer, and removing the dummy substrates. The first redistribution layer may be electrically connected to the second redistribution layer utilizing a conductive pillar. An encapsulant material may be formed between the first and second redistribution layers. Side portions of one of the first and second redistribution layers may be covered with encapsulant. A surface of the semiconductor die may be in contact with the second redistribution layer. The dummy substrates may be in panel form. One of the dummy substrates may be in panel form and the other in unit form.

This disclosure relates to a multilayer structure containing: a substrate; a coupling layer deposited on the substrate; and a dielectric layer deposited on the coupling layer, wherein shear strength is increased by a factor of at least about 2 in the presence of the coupling layer compared to a multilayer in the absence of the coupling layer.

Embodiments described herein provide techniques for forming a solder mask having a repeating pattern of features formed therein. The repeating pattern of features can be conceptually understood as a plurality of groove structures formed in the solder mask. The solder mask can be included in a semiconductor package that comprises the solder mask over a substrate and a molding compound over the solder mask that conforms to the repeating pattern of features. Several advantages are attributable to embodiments of the solder mask described herein. One advantage is that the repeating pattern of features formed in the solder mask increase the contact area between the solder mask and the molding compound. Increasing the contact area can assist with increasing adherence and conformance of the molding compound to the solder mask. This increased adherence and conformance assists with minimizing or eliminating interfacial delamination.

In some examples, a package comprises a semiconductor die and a bond pad formed upon the semiconductor die. The bond pad has a protrusion on a top surface of the bond pad. The package also comprises a metal contact and a bond wire coupled to the protrusion and to the metal contact.

A manufacturing method of a chip package structure includes the following steps. A plurality of chips is disposed on a first insulating layer. The back surface of each of the chips is in direct contact with the first insulating layer. A stress buffer layer is formed to extend and cover the active surface and the peripheral surface of each of the chips, and a bottom surface of the stress buffer layer is aligned with the back surface of each of the chips. The stress buffer layer has an opening exposing a part of the active surface of each of the chips, and the redistribution layer is electrically connected to each of the chips through the opening. A plurality of solder balls is electrically connected to the redistribution layer exposed by the blind holes. A singularizing process is performed to form a plurality of chip package structures separated from each other.