A component package includes a printed circuit board; a first electronic component disposed in a first region on the printed circuit board; a second electronic component disposed in a second region on the printed circuit board; and a metal wall disposed on the printed circuit board and spatially partitioning the first region and the second region on a plane. The metal wall is directly connected to the printed circuit board.

A semiconductor package comprises a lead frame, a die pad, bond pads, and leads. A die may be arranged on the die pad, the die comprising an integrated circuit. In an example, the die and at least a portion of the lead frame are encapsulated with a molding compound (MC). A first thickness of the MC over a first portion of the die is less than a second thickness over a second portion of the die to form a cavity in the MC and the MC directly contacts the first portion and the second portion of the die.

A method includes attaching an integrated circuit die adjacent to a first substrate, the integrated circuit die comprising: an active device in a second substrate; a pad adjacent to the second substrate; and a first dielectric layer adjacent to the second substrate, the first dielectric layer comprising a polyimide with an ester group; forming an encapsulant around the integrated circuit die; and removing the first dielectric layer.

A semiconductor device includes a first semiconductor die mounted on a substrate, a second semiconductor die mounted on the substrate and separated from the first semiconductor die, a first dielectric material between the first semiconductor die and the second semiconductor die and having a first density, and a column of second dielectric material in the first dielectric material, the second dielectric material having a second density different than the first density, and the second dielectric material including a void region.

A chip includes a semiconductor substrate, an electrical connector over the semiconductor substrate, and a molding compound molding a lower part of the electrical connector therein. A top surface of the molding compound is lower than a top end of the electrical connector. A recess extends from the top surface of the molding compound into the molding compound.

An embodiment method for forming a semiconductor package includes attaching a first die to a first carrier, depositing a first isolation material around the first die, and after depositing the first isolation material, bonding a second die to the first die. Bonding the second die to the first die includes forming a dielectric-to-dielectric bond. The method further includes removing the first carrier and forming fan-out redistribution layers (RDLs) on an opposing side of the first die as the second die. The fan-out RDLs are electrically connected to the first die and the second die.

A package structure includes a circuit substrate, a package element and a molding layer. The package element is disposed on the circuit substrate and is electrically connected with the circuit substrate. The molding layer is disposed over the circuit substrate and covers at least a top surface of the circuit substrate. The molding layer includes a first portion wrapping around sidewalls of the package element and having a first thickness, and a second portion surrounding the first portion and connected with the first portion. The first thickness of the first portion is larger than a second thickness of the second portion. A top surface of the first portion of the molding layer is higher than a top surface of the package element.

A package that includes a substrate, an integrated device, a first encapsulation layer and a void. The substrate includes a first surface. The integrated device is coupled to the first surface of the substrate. The first encapsulation layer is located over the first surface of the substrate and the integrated device. The first encapsulation layer includes an undercut relative to a side surface of the integrated device. The void is located between the integrated device and the first surface of the substrate. The void is laterally surrounded by the undercut of the encapsulation layer.

A semiconductor device includes: a semiconductor element, a first lead frame, a second lead frame, and a thermally conductive member; and a sealing member sealing them. The first lead frame includes: a first portion exposed from a first side surface of the sealing member; and a second portion located closer to a lower surface of the sealing member than the first portion in a second direction crossing the lower surface. The semiconductor device further includes an intermediate frame which is located between the second portion and the fifth portion at least in the second direction. A distance, in the first direction, between the second portion and the intermediate frame is shorter than a distance, in the second direction, between an upper surface of the first portion and the upper surface of the second portion.

A method of manufacturing a component carrier includes: (i) embedding a poorly adhesive structure in a stack, wherein the stack comprises at least one electrically conductive layer structure and/or at least one electrically insulating layer structure; (ii) forming a cavity in the stack by removing a stack piece, wherein the stack piece is in part delimited by the poorly adhesive structure; and (iii) selectively exposing a bottom of the cavity by partially removing the poorly adhesive structure. A corresponding component carrier includes analogous features.