This invention relates to an external secure and encrypted SSD device that achieves the high write and read speed and storage volume of larger devices. This invention also relates to an external SSD device with an operating system wherein the operating system is booted up through the firmware of the external SSD device rather than through the operating system of an external computer.

An electronic component includes a mold layer and a semiconductor die including a low ohmic first portion and a high ohmic second portion. The low ohmic first portion has an active area. The high ohmic second portion is arranged on the mold layer.

A semiconductor module is provided, including: a semiconductor chip having an upper surface electrode and a lower surface electrode opposite to the upper surface electrode; a metal wiring plate electrically connected to the upper surface electrode of the semiconductor chip; and a sheet-like low elastic sheet provided on the metal wiring plate, the low elastic sheet having elastic modulus lower than that of the metal wiring plate. A manufacturing method for a semiconductor module is provided, including: providing a semiconductor chip; solder-bonding a metal wiring plate above said semiconductor chip; and applying a sheet-like low elastic sheet having the elastic modulus lower than that of said metal wiring plate to said metal wiring plate.

The invention relates to a foil-based package having at least one foil substrate having an electrically conductive layer arranged thereon, at least one electronic device having a device terminal pad having at least one device terminal pad, and a plurality of package terminal pads arranged on a package terminal side. The foil substrate includes a first foil portion and a second foil portion, the first foil portion extending along a first foil plane and the second foil portion extending along a second foil plane parallel to the first foil plane, the first foil plane and the second foil plane being offset relative to each other so that the foil substrate forms a recess within which the at least one electronic device is arranged.

A foil-based package and a method for manufacturing a foil-based package includes, among other things, a first and a second foil substrate. An electronic component is arranged between the two foil substrates in a sandwich-like manner. Due to the component thickness, there is a distance difference between the two foil substrates between the mounting area of the component and ears outside of the mounting area. The foil-based package and the method provides means for reducing and/or compensating a distance difference between the first foil substrate and the second foil substrate caused by the component thickness.

A method of making a semiconductor device may include providing a carrier comprising a semiconductor die mounting site. A build-up interconnect structure may be formed over the carrier. A first portion of a conductive interconnect may be formed over the build-up interconnect structure in a periphery of the semiconductor die mounting site. An etch stop layer and a second portion of the conductive interconnect may be formed over the first portion of the conductive interconnect. A semiconductor die may be mounted to the build-up interconnect at the semiconductor die mounting site. The conductive interconnect and the semiconductor die may be encapsulated with a mold compound. A first end of the conductive interconnect on the second portion of the conductive interconnect may be exposed. The carrier may be removed to expose the build-up interconnect structure. The first portion of the conductive interconnect may be etched to expose the etch stop layer.

Described is an apparatus which comprises: a die having a first side and a second side opposite to the first side; a die backside film (DBF) or die attach film (DAF) disposed over the first side of the die; and a fluorocarbon layer disposed over the DBF or DAF. Described is a method which comprises: applying a die backside film (DBF) over a first side of a die, wherein the die has a second side which metal bumps; and applying a plasma polymerization process to treat the DBF with a fluorocarbon plasma.

A semiconductor module can comprise a fully molded base portion comprising a planar surface that further comprises a semiconductor die comprising contact pads, conductive pillars coupled to the contact pads and extending to the planar surface, and an encapsulant material disposed over the active surface, four side surfaces, and around the conductive pillars, wherein ends of the conductive pillars are exposed from the encapsulant material at the planar surface of the fully molded base portion. A build-up interconnect structure comprising a routing layer can be disposed over the fully molded base portion. A photo-imagable solder mask material can be disposed over the routing layer and comprise openings to form surface mount device (SMD) land pads electrically coupled to the semiconductor die and the conductive pillars. A SMD component can be electrically coupled to the SMD land pads with surface mount technology (SMT).

A semiconductor module can comprise a fully molded base portion comprising a planar surface that further comprises a semiconductor die comprising contact pads, conductive pillars coupled to the contact pads and extending to the planar surface, and an encapsulant material disposed over the active surface, four side surfaces, and around the conductive pillars, wherein ends of the conductive pillars are exposed from the encapsulant material at the planar surface of the fully molded base portion. A build-up interconnect structure comprising a routing layer can be disposed over the fully molded base portion. A photo-imagable solder mask material can be disposed over the routing layer and comprise openings to form surface mount device (SMD) land pads electrically coupled to the semiconductor die and the conductive pillars. A SMD component can be electrically coupled to the SMD land pads with surface mount technology (SMT).

A semiconductor device may comprise a semiconductor die comprising an active surface and contact pads disposed. Conductive interconnects comprising first ends may be coupled to the contact pads and second ends may be disposed opposite the first ends. An encapsulant may comprise a planar surface disposed over the active surface of the semiconductor die. The planar surface may be offset from the second surface of the conductive interconnects by a distance greater than or equal to 1 micrometer. A build-up interconnect layer may be disposed over the planar surface and extend into the openings to electrically connect with the conductive interconnects. A method of making the semiconductor device may further comprise grinding a surface of the encapsulant to form the planar surface and the conductive residue across the planar surface. The conductive residue may be etched to remove the conductive residue and to reduce a height of the conductive interconnects.