The present application provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a semiconductor substrate, a heterojunction structure, a cap layer, a first passivation layer and a second passivation layer disposed from bottom to up; a trench penetrating through the first passivation layer and the second passivation layer; and a P-type semiconductor layer located at least on an inner wall of the trench. After a part of the second passivation layer is dry etched to form the trench, the first passivation layer can be used for etching endpoint detection to avoid over etching. A part of the first passivation layer exposed by the trench of the second passivation layer can be removed by wet etching. When the exposed part of the first passivation layer is removed by the wet etching, due to the cap layer has extremely high stability, after the exposed part of the first passivation layer is removed by the wet etching, the cap layer will not be damaged. The non-damaged cap layer can effectively reduce surface defects of the heterojunction structure to decrease a probability of electrons being trapped by the defects, thereby weakening a current collapse effect and reducing a dynamic on-resistance.

Curing of a passivation layer applied to the surface of a ferroelectric integrated circuit so as to enhance the polarization characteristics of the ferroelectric structures. A passivation layer, such as a polyimide, is applied to the surface of the ferroelectric integrated circuit after fabrication of the active devices. The passivation layer is cured by exposure to a high temperature, below the Curie temperature of the ferroelectric material, for a short duration such as on the order of ten minutes. Variable frequency microwave energy may be used to effect such curing. The cured passivation layer attains a tensile stress state, and as a result imparts a compressive stress upon the underlying ferroelectric material. Polarization may be further enhanced by polarizing the ferroelectric material prior to the cure process.

A multi-pin wafer level chip scale package is achieved. One or more solder pillars and one or more solder blocks are formed on a silicon wafer wherein the one or more solder pillars and the one or more solder blocks all have a top surface in a same horizontal plane. A pillar metal layer underlies the one or more solder pillars and electrically contacts the one or more solder pillars with the silicon wafer through an opening in a polymer layer over a passivation layer. A block metal layer underlies the one or more solder blocks and electrically contacts the one or more solder pillars with the silicon wafer through a plurality of via openings through the polymer layer over the passivation layer wherein the block metal layer is thicker than the pillar metal layer.

An electronic device is provided. The electronic device includes at least two non-recesses, a recess and an organic layer. The recess is disposed between the at least two non-recesses. The at least two non-recesses and the recess are formed in an insulating layer. The organic layer is disposed on the at least two non-recesses and in the recess. The organic layer includes an end which is in contact with one of the at least two non-recesses.

An electronic power device includes a substrate of silicon carbide (SiC) having a front surface and a rear surface which lie in a horizontal plane and are opposite to one another along a vertical axis. The substrate includes an active area, provided in which are a number of doped regions, and an edge area, which is not active, distinct from and surrounding the active area. A dielectric region is arranged above the front surface, in at least the edge area. A passivation layer is arranged above the front surface of the substrate, and is in contact with the dielectric region in the edge area. The passivation layer includes at least one anchorage region that extends through the thickness of the dielectric region at the edge area, such as to define a mechanical anchorage for the passivation layer.

A method of manufacturing a semiconductor device includes: forming a conductive pad region over a substrate; depositing a dielectric layer over the conductive pad region; forming a first passivation layer over the dielectric layer; etching the first passivation layer through the dielectric layer, thereby exposing a first area of the conductive pad region; forming a second passivation layer over the first area of the conductive pad region; and removing portions of the second passivation layer to expose a second area of the conductive pad region.

Hydrophobic, tough, photoimageable, functionalized polyimide formulations have been discovered that can be UV cured and developed in cyclopentanone. The present invention formulations can be used as passivation and redistribution layers with patterning provided by photolithograph, for the redistribution of I/O pads on fan-out RDL applications. The curable polyimide formulations reduce stress on thin wafers, when compared to conventional polyimide formulations, and provide low modulus, hydrophobic solder mask. These materials can serve as protective layers in any applications in which a thin, flexible, and hydrophobic polymer is required, that also has high tensile strength and high elongation at break.

A method of fabricating a semiconductor device includes providing a GaN substrate with an epitaxial layer formed thereover, the epitaxial layer forming a heterojunction with the GaN substrate, the heterojunction supporting a 2-dimensional electron gas (2DEG) channel in the GaN substrate. A composite surface passivation layer is formed over a top surface of the epitaxial layer, wherein the composite surface passivation layer comprises a first passivation layer portion formed proximate to a first region of the GaN device and a second passivation layer portion formed proximate to a second region of the GaN device. The first and second passivation layer portions are disposed laterally adjacent to each other over the epitaxial layer, wherein the first passivation layer portion is formed in a first process and the second passivation layer portion is formed in a second process.

A semiconductor chip includes a semiconductor substrate including a device region, and an edge region surrounding the device region, a device layer on the semiconductor substrate, a wiring layer on the device layer, a side surface of the wiring layer at least partially defining a recessed region that is in the edge region such that the side surface of the wiring layer is exposed by the recessed region, and an upper insulating layer on the wiring layer. The recessed region extends from a side surface of the device layer toward the device region. A first portion of the upper insulating layer covers the side surface of the wiring layer that is exposed by the recessed region.

In some examples, a semiconductor package includes a semiconductor die; a passivation layer abutting a device side of the semiconductor die; a first conductive layer abutting the device side of the semiconductor die; a second conductive layer abutting the first conductive layer and the passivation layer; a silicon nitride layer abutting the second conductive layer, the silicon nitride layer having a thickness ranging from 300 Angstroms to 3000 Angstroms; and a third conductive layer coupled to the second conductive layer at a gap in the silicon nitride layer, the third conductive layer configured to receive a solder ball.