A cathode configured for a solid-state battery includes a body having grains of inorganic material sintered to one another, wherein the grains comprise lithium. A thickness of the body is from 3 μm to 100 μm. The first major surface and the second major surface have an unpolished granular profile such that the profile includes grains protruding outward from the respective major surface with a height of at least 25 nm and no more than 150 μm relative to recessed portions of the respective major surface at boundaries between the respective grains.

A vapor chamber structure includes a main body formed of a metal plate and a ceramic plate. The metal plate and the ceramic plate are closed to each other to define a chamber therebetween; and the chamber is internally provided with a wick structure, a support structure, and a working fluid. The metal plate and the ceramic plate are connected to each other via welding or a direct bonding copper process, and the support structure is connected to between the metal plate and the ceramic plate also via welding or the direct bonding copper process. By contacting the ceramic plate of the vapor chamber with a heat source packaged in a ceramic material to transfer heat, the problem of crack at an interface between the vapor chamber and the heat source due to thermal fatigue can be overcome.

A thermal interface material for forming a layer conformable between a first heat transfer surface and an opposing second heat transfer surface to provide a thermal pathway therebetween includes: a matrix material composing 10 wt. % or less of the thermal interface material; a filler dispersed in the matrix material composing at least 80 wt. % of the thermal interface material, the filler including: particles of a first material having a nominal dimension in a range from 1 micron to 100 microns, the first material composing at least 40 wt. % of the thermal interface material; and diamond particles having a nominal dimension of 1,000 nm or less, the diamond particles composing 0.5 wt. % to 5 wt. % of the thermal interface material.

A method includes forming a transistor over a front side of a substrate, in which the transistor comprises a channel region, a gate region over the channel region, and source/drain regions on opposite sides of the gate region; forming a front-side interconnect structure over the transistor, wherein the front-side interconnect structure includes a dielectric layer and conductive features; and bonding the front-side interconnect structure to a carrier substrate via a bonding layer, in which the bonding layer is between the front-side interconnect structure and the carrier substrate, and the bonding layer has a higher thermal conductivity than the dielectric layer of the front-side interconnect structure.

A frame is made of a first material. An external terminal electrode is attached to the frame. A heat sink plate supports the frame and includes a mounting region in the frame. The heat sink plate is made of a non-composite material containing copper with purity of 95.0 weight percentage or more. A first adhesive layer bonds the frame and the heat sink plate to each other. The first adhesive layer is made of a second material different from the first material, and has a first composition. A power semiconductor element is mounted on the mounting region of the heat sink plate. A cover is attached to the frame to constitute a sealing space sealing the power semiconductor element without gross leak. A second adhesive layer bonds the frame and the cover to each other, and has a second composition different from the first composition of the first adhesive layer.

A semiconductor module has a heat conduction section provided between a multilayer substrate, on which semiconductor chips are mounted, and a cooler. The heat conduction section includes a frame and an opening, and the opening has a grease portion which is provided partly in the opening and is in contact with the multilayer substrate and the cooler, and a space portion which is provided between the grease portion and the frame in a partial and band-shaped manner.

One embodiment of the present invention relates to a thermally conductive sheet containing graphite particles (A) including at least one selected from the group consisting of flake-like particles, ellipsoidal particles, and cylindrical particles, in which the graphite particles (A) are oriented in a thickness direction, and a thickness compression ratio is 24% or more at a temperature of 150° C. and a compressive stress of 0.14 MPa.

A heat-insulation device and an electronic product, the heat-insulation device is of a closed hollow structure, and includes a first cover body and a second cover body arranged opposite to each other; a vacuum cavity is formed in the heat-insulation device; the first cover body is made of a heat-conducting material; and a heat-conducting element is provided in the vacuum cavity, and a first end of the heat-conducting element is in contact with an inner wall surface of the first cover body.

The present invention provides a packaging method and a packaging structure for a cascode power electronic device, in which a hetero-multiple chip scale package is used to replace the traditional die bonding and wire bonding packaging method. The cascode power electronic device can reduce the inductance resistance and thermal resistance of the connecting wires and reduce the size of the package; and increase the switching frequency of power density. The chip scale package of the present invention uses more than one gallium nitride semiconductor die, more than one diode, and more than one metal oxide semiconductor transistor. The package structure can use TO-220, quad flat package or other shapes and sizes; the encapsulation process of the traditional epoxy molding compounds can be used in low-power applications; and the encapsulation process of ceramic material can be used in high-power applications.

A memory device including a first semiconductor die and a memory cube mounted on and connected with the first semiconductor die is described. The memory cube includes multiple stacked tiers, and each tier of the multiple stacked tiers includes second semiconductor dies laterally wrapped by an encapsulant and a redistribution structure disposed on the second semiconductor dies and the encapsulant. The second semiconductor dies of the multiple stacked tiers are electrically connected with the first semiconductor die through the redistribution structures in the multiple stacked tiers. Each redistribution structure in the multiple stacked tiers includes redistribution patterns, the redistribution structure closest to the first semiconductor die further includes a thermally conductive layer connected to the first semiconductor die, wherein a material of the redistribution patterns in the multiple stacked tiers is different from a material of the thermally conductive layer of the redistribution structure closest to the first semiconductor die, and the thermally conductive layer is electrically isolated from the second semiconductor dies in the multiple stacked tiers and the first semiconductor die.