A method and structure for packaging a semiconductor device are provided. In an embodiment a first substrate is bonded to a second substrate, which is bonded to a third substrate. A thermal interface material is placed on the second substrate prior to application of an underfill material. A ring can be placed on the thermal interface material, and an underfill material is dispensed between the second substrate and the third substrate. By placing the thermal interface material and ring prior to the underfill material, the underfill material cannot interfere with the interface between the thermal interface material and the second substrate, and the thermal interface material and ring can act as a physical barrier to the underfill material, thereby preventing overflow.

A 3D integrated circuit device, including: a first transistor; a second transistor; and a third transistor, where the third transistor is overlaying the second transistor and the third transistor is controlled by a third control line, where the second transistor is overlaying the first transistor and the second transistor is controlled by a second control line, where the first transistor is part of a control circuit controlling the second control line and the third control line, and where the second transistor and the third transistor are self-aligned.

An inner fin is a wave fin having board portions extending in a pipe longitudinal direction and a top portion connecting the board portions located adjacent with each other. The wave fin has a wave-shaped cross-section perpendicularly intersecting a pipe longitudinal direction, and the board portion is bent into a waveform extending in the pipe longitudinal direction when seen from a pipe layering direction. A wave pitch WP [mm], a wave depth WD [mm], and a passage width H [mm] are set to satisfy relationships of 2.2≤WP/WD≤4.28 and 0.5≤WD/H≤1.8.

A system includes a retainer assembly to align each of a group of cooling devices with a corresponding electrical component of a group of electrical components that are mounted to a circuit board, where the retainer assembly includes a group of apertures, such that each of the cooling devices protrudes through a corresponding aperture when the retainer assembly is installed on the circuit board, and where the retainer assembly includes a group of retaining springs, each of which is associated with a corresponding aperture, that applies a respective force, of a group of forces, to a corresponding one of the cooling devices when the retainer assembly is installed on the circuit board. The system also includes a set of fasteners to mount the retainer assembly to the circuit board, such that the cooling devices dissipate heat that is generated by the electrical components.

In order to efficiently cool a heat-generating semiconductor element, it is desirable to cool a power semiconductor element from both surfaces. Therefore, in order to cool multiple power semiconductor elements, it is an effective way to alternately arrange a semiconductor component having the incorporated semiconductor element and a cooling device. A power conversion device for handling a high-power voltage needs to ensure pressure resistance between semiconductor elements or circuits inside the device. It is an effective way to seal the semiconductor component with a sealing material such as a silicone gel. Therefore, it is necessary to install the semiconductor component or the circuit having the incorporated semiconductor element, in a case from which a liquid silicone gel prior to curing does not leak even if the gel is injected. For these reasons, an object to be achieved by the invention is that the semiconductor element can be cooled from both surfaces by alternately arranging the semiconductor component having the incorporated semiconductor element and the cooling device. The above-described object can be achieved as follows. A substantially rectangular thin plate is subjected to mountain bending and valley bending so as to form a shape having as many recesses as the number of the mounted semiconductor components having the incorporated semiconductor element. Concurrently, a lateral side in a direction orthogonal to the above-described bending direction is bent so as to dispose the case in which all edges configuring an outer shape of the thin plate are arranged on substantially the same plane. The semiconductor component having the incorporated semiconductor element is arranged at a position serving as the recess of the case. The cooling devices are arranged so as to interpose the semiconductor component having the incorporated semiconductor element via the case. The semiconductor component having the incorporated semiconductor element is sealed with a silicone gel. In addition, preferably, the case is configured to include metal which has high heat conductivity. More preferably, the case is configured to include aluminum, copper, or an alloy whose principal components are both of these.

Semiconductor device assemblies with heat transfer structures formed from semiconductor materials are disclosed herein. In one embodiment, a semiconductor device assembly can include a thermal transfer structure formed from a semiconductor substrate. The thermal transfer structure includes an inner region, an outer region projecting from the inner region, and a cavity defined in the outer region by the inner and outer regions. The semiconductor device assembly further includes a stack of first semiconductor dies in the cavity, and a second semiconductor die attached to the outer region of the thermal transfer structure and enclosing the stack of first semiconductor dies within the cavity.

A semiconductor device includes: multiple semiconductor elements each having a one surface and a rear surface in a plate thickness direction; a first member that sandwiches the multiple semiconductor elements and is electrically connected to an electrode on the one surface; a second member electrically connected to an electrode on the rear surface; and multiple terminals that are continuous from the first or second member. An area of the second member is smaller than that of the first member. Semiconductor elements are arranged in a longitudinal direction of the second member. The semiconductor device further includes a first joint portion that electrically connects each semiconductor element and the second member and a second joint portion that electrically connects a terminal and the second member. The multiple solder joint portions are symmetrically placed.

A semiconductor package includes a redistribution structure, a memory wafer, semiconductor dies and conductive vias. The memory wafer, disposed over the redistribution structure, includes at least one memory die. The semiconductor dies are disposed side by side with respect to each other, between the memory wafer and the redistribution structure, and are electrically connected to the redistribution structure. The conductive vias electrically connect the at least one memory die with the redistribution structure. A semiconductor package includes a redistribution structure, a reconstructed wafer, and a heat sink. The reconstructed wafer is disposed on the redistribution structure. The reconstructed wafer includes logic dies and memory dies. The logic dies are electrically connected to the redistribution structure. The memory dies are electrically connected to the redistribution structure and vertically stacked with the logic dies. The heat sink is disposed on the reconstructed wafer. The heat sink is fastened to the reconstructed wafer.

A package includes a first package and a second package over and bonded to the first package. The first package includes a first device die, and a first encapsulant encapsulating the first device die therein. The second package includes an Independent Passive Device (IPD) die, and a second encapsulant encapsulating the IPD die therein. The package further includes a power module over and bonded to the second package.

A semiconductor package device includes a package substrate, an interposer on the package substrate, a semiconductor package on the interposer, and an under-fill between the interposer and the semiconductor package. The interposer includes at least one first trench at an upper portion of the interposer that extends in a first direction parallel to a top surface of the package substrate. The at least one first trench vertically overlaps an edge region of the semiconductor package. The under-fill fills at least a portion of the at least one trench.