Patent classifications
H01L23/4012
PRESSURE BALANCING CLAMP FOR PRESS-PACK INSULATED GATE BIPOLAR TRANSISTOR MODULE
Disclosed is a pressure balancing clamp for a press-pack insulated gate bipolar transistor (IGBT) module. The pressure balancing clamp for a press-pack IGBT module includes a bracket, where the bracket is provided with two longitudinally arranged pressure equalizing plates in a sliding way; the pressure equalizing plates are connected through pressure sensors; the upper and lower ends inside the bracket are respectively connected with the pressure equalizing plates through hydraulic devices and a displacement compensation device; opposite surfaces of the two pressure equalizing plates are respectively provided with heat dissipation and confluence devices. The pressure sensors are in one-to-one correspondence with the hydraulic devices and are electrically connected. The hydraulic devices adjust the pressure according to the readings of the pressure sensors in corresponding directions, so that the pressure of the press-pack IGBT module is balanced.
SEMICONDUCTOR PACKAGES AND METHODS OF FORMING THE SAME
A semiconductor package includes a circuit board structure, a first redistribution layer structure and first bonding elements. The circuit board structure includes outermost first conductive patterns and a first mask layer adjacent to the outermost first conductive patterns. The first redistribution layer structure is disposed over the circuit board structure. The first bonding elements are disposed between and electrically connected to the first redistribution layer structure and the outermost first conductive patterns of the circuit board structure. In some embodiments, at least one of the first bonding elements covers a top and a sidewall of the corresponding outermost first conductive pattern.
Semiconductor device and method of manufacturing semiconductor device
An object of the present invention is to provide a semiconductor device whose surfaces on both sides can be cooled and which has a function of insulating, on both the surfaces, the internal structure of a semiconductor package from the outside. The semiconductor device includes a first semiconductor package and a second semiconductor package. The second semiconductor package is joined on the first semiconductor package in such a manner that a first exposed surface of the first semiconductor package and a fourth exposed surface of the second semiconductor package are connected so as to face each other, and a second exposed surface of the first semiconductor package and a third exposed surface of the second semiconductor package are connected so as to face each other.
Plurality of cooling tubes with coolant for a power conversion package
A power conversion apparatus includes a semiconductor element, a plurality of lead frames, a flow-passage formation body, an insulating portion, a metal joining material, and a resin sealing portion. The plurality of lead frames are electrically connected to the semiconductor element. The flow-passage formation body forms a coolant flow passage in which a coolant flows. The insulating portion is arranged between the lead frame and the flow-passage formation body to provide insulation between the lead frame and the flow-passage formation body. The metal joining material joins the insulating portion and the flow-passage formation body. The resin sealing portion seals the semiconductor element and the lead frames. The semiconductor element and the lead frames are integrated with the flow-passage formation body to form a semiconductor cooling assembly by the resin sealing portion.
Electric power conversion apparatus
In an electric power conversion apparatus, a semiconductor module-cooler unit includes a semiconductor module and a cooler that has cooling pipes stacked with the semiconductor module in a stacking direction. A flow path forming component includes an electronic component main body and has an in-component flow path formed therein. A case receives both the semiconductor module-cooler unit and the flow path forming component therein. A pressure-applying member is arranged in the case to apply pressure to the semiconductor module-cooler unit from a rear side toward a front side in the stacking direction. Moreover, the flow path forming component is fixed to the case. The pressure-applying member, the semiconductor module-cooler unit and the flow path forming component are arranged in alignment with each other in the stacking direction. An in-cooler flow path formed in the cooler and the in-component flow path are fluidically connected with each other in the stacking direction.
SEMICONDUCTOR DEVICE
A semiconductor device includes a heat dissipation member, multiple switching elements, and multiple signal terminals. The switching elements include a first switching element formed on a silicon substrate and a second switching element formed on a silicon carbide substrate, and include at least one of the first switching element or the second switching element in a plural number Each of the switching elements includes a temperature sense pad. The first switching element and the second switching element are alternately arranged in a predetermined direction in which a refrigerant flows. In the switching elements of same type as the switching element disposed on a most downstream side in the predetermined direction, the signal terminal corresponding to the temperature sense pad is provided for the switching element disposed on the most downstream side, and is not provided for the switching elements disposed on more upstream side.
SEMICONDUCTOR PACKAGES AND METHODS OF FORMING THE SAME
A semiconductor package includes a circuit board structure, a first redistribution layer structure and first bonding elements. The circuit board structure includes outermost first conductive patterns and a first mask layer adjacent to the outermost first conductive patterns. The first redistribution layer structure is disposed over the circuit board structure. The first bonding elements are disposed between and electrically connected to the first redistribution layer structure and the outermost first conductive patterns of the circuit board structure. In some embodiments, at least one of the first bonding elements covers a top and a sidewall of the corresponding outermost first conductive pattern.
MOLDED SEMICONDUCTOR PACKAGE HAVING A NEGATIVE STANDOFF
A molded semiconductor package includes a mold compound, a plurality of leads each having a first end embedded in the mold compound and a second end protruding from a side face of the mold compound, and a semiconductor die embedded in the mold compound and electrically connected, within the mold compound, to the plurality of leads. The second end of each lead of the plurality of leads has a bottom surface facing in a same direction as a bottom main surface of the mold compound. Each lead of the plurality of leads has a negative standoff relative to the bottom main surface of the mold compound.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
An object of the present invention is to provide a semiconductor device whose surfaces on both sides can be cooled and which has a function of insulating, on both the surfaces, the internal structure of a semiconductor package from the outside. The semiconductor device includes a first semiconductor package and a second semiconductor package. The second semiconductor package is joined on the first semiconductor package in such a manner that a first exposed surface of the first semiconductor package and a fourth exposed surface of the second semiconductor package are connected so as to face each other, and a second exposed surface of the first semiconductor package and a third exposed surface of the second semiconductor package are connected so as to face each other.
Integrated circuits and methods for forming integrated circuits
An example relates to an integrated circuit including a semiconductor substrate, and a wiring layer stack located on the semiconductor substrate. The integrated circuit further includes a transistor embedded in the wiring layer stack. The transistor includes an embedded layer. The embedded layer has a thickness of less than 10 nm. The embedded layer includes at least one two-dimensional crystalline layer including more than 10% metal atoms. Further examples relate to methods for forming integrated circuits.