A method includes forming a solder layer on a surface of one or more chips. A lid is positioned over the solder layer on each of the one or more chips. Heat and pressure are applied to melt the solder layer and attach each lid to a corresponding solder layer. The solder layer has a thermal conductivity of ≥50 W/mK.

A power electronics module includes a glass layer with one or more vias extending through the glass layer and having an electrically and thermally conductive material disposed within the one or more vias, a power electronic device directly bonded to a first surface of the glass layer, and, a cooling structure thermally coupled to a second surface of the glass layer.

A heat dissipation structure includes a heat dissipation portion and a heat storage portion. The heat dissipation portion has the heat receiving surface including the contact surface in contact with the semiconductor generating the heat, and dissipates the heat of the semiconductor in contact with the contact surface. The heat storage portion is arranged to sandwich the semiconductor. The heat storage portion has, for example, the heat storage opening portion in which the semiconductor is positioned, and surrounds the semiconductor. The heat storage portion is provided to he in contact with the heat receiving surface, and stores the heat of the semiconductor conducted through the heat dissipation portion.

A semiconductor package includes a semiconductor chip; a redistribution insulating layer including a first opening; an external connection bump including a first part in the first opening; a lower bump pad including a first surface in physical contact with the first part of the external connection bump and a second surface opposite to the first surface, wherein the first surface and the redistribution insulating layer partially overlap; and a redistribution pattern that electrically connects the lower bump pad to the semiconductor chip.

A Thermal Interface Material (TIM) for chip warpage may be provided. A system may comprise an Integrated Circuit (IC) chip, a Thermal Interface Material (TIM) layer disposed on the IC chip, and a heatsink disposed on the TIM layer. The heatsink may comprise, a plate, a plurality of fins, and at least one TIM storage chamber disposed in the plate between two of the plurality of fins. The at least one TIM storage chamber may be filled with a TIM that is solid at a lower temperature end of a thermal cycle of the IC chip and that is liquid at a higher temperature end of the thermal cycle of the IC chip.

A semiconductor package includes a redistribution substrate having first and second surfaces, and an insulating member and a plurality of redistribution layers on different levels in the insulating member and electrically connected together; a plurality of under bump metallurgy (UBM) pads in the insulating member and connected to a redistribution layer, among the plurality of redistribution layers, adjacent to the first surface, the UBM pads having a lower surface exposed to the first surface of the redistribution substrate; a dummy pattern between the UBM pads in the insulating member, the dummy pattern having a lower surface located at a level higher than the lower surface of the UBM pads; and at least one semiconductor chip on the second surface of the redistribution substrate and having a plurality of contact pads electrically connected to a redistribution layer, among the plurality of redistribution layers, adjacent to the second surface.

The invention is directed to a novel solution to providing heat management and cooling to electronic devices. According to various embodiments, heat produced during the operation of the processing components in the computing device is absorbed by heat management features integrated within a supporting mid-frame. The heat management features include phase changing materials that allow the processing components to be kept at a isothermal state through changes in phase, thereby prolonging the duration of time in which the processing components can operate at high performance levels without the need to throttle the performance.

Disclosed is a semiconductor package comprising a package substrate having a mount region and a peripheral region that surrounds the mount region, a semiconductor device on the mount region of the package substrate, a package cap on the peripheral region of the package substrate and including a partition portion that surrounds the semiconductor device and an extension portion that covers the semiconductor device, and an adhesive layer between the package substrate and a bottom surface of the package cap. The bottom surface of the package cap has a trench. The trench has a trapezoidal cross-section whose width decreases in a direction receding from the bottom surface of the package cap. The adhesive layer is in contact with a top surface of the package substrate and the bottom surface of the package cap. The adhesive layer fills the trench.

An Integrated Circuit (IC) assembly, comprising an IC package coupled to a substrate, and a subassembly comprising a thermal interface layer. The thermal interface layer comprises a phase change material (PCM) over the IC package. At least one thermoelectric cooling (TEC) apparatus is thermally coupled to the thermal interface layer.

A thermal management unit includes a heat sink, which includes a base portion having a first side and a second side opposite the first side. The heat sink also includes a first protrusion structure and a second protrusion structure. The first protrusion structure protrudes from the first side of the base portion, and the first protrusion structure includes a plurality of fins. The second protrusion structure protrudes from the second side of the base portion, and the second protrusion structure includes a plurality of ribs.