SEMICONDUCTOR PACKAGE

Abstract

A semiconductor package includes a redistribution substrate having first and second surfaces, and an insulating member and a plurality of redistribution layers on different levels in the insulating member and electrically connected together; a plurality of under bump metallurgy (UBM) pads in the insulating member and connected to a redistribution layer, among the plurality of redistribution layers, adjacent to the first surface, the UBM pads having a lower surface exposed to the first surface of the redistribution substrate; a dummy pattern between the UBM pads in the insulating member, the dummy pattern having a lower surface located at a level higher than the lower surface of the UBM pads; and at least one semiconductor chip on the second surface of the redistribution substrate and having a plurality of contact pads electrically connected to a redistribution layer, among the plurality of redistribution layers, adjacent to the second surface.

Claims

1. A semiconductor package, comprising: a redistribution substrate having first and second surfaces, disposed opposite to each other, the redistribution substrate including an insulating member and a plurality of redistribution layers disposed on a plurality of different levels in the insulating member, respectively, and electrically connected to each other; a plurality of under-bump metallurgy (UBM) pads disposed in the insulating member and electrically connected to a redistribution layer, among the plurality of redistribution layers, that is adjacent to the first surface of the redistribution substrate, the plurality of UBM pads having lower surfaces exposed to the first surface of the redistribution substrate; a dummy pattern disposed between the plurality of UBM pads in the insulating member, the dummy pattern having a lower surface located on a level higher than the lower surfaces of the plurality of UBM pads; and at least one semiconductor chip disposed on the second surface of the redistribution substrate and having a plurality of contact pads electrically connected to a redistribution layer, among the plurality of redistribution layers, adjacent to the second surface of the redistribution substrate, wherein: the insulating member includes a first insulating film covering a first portion of a side surface of the plurality of UBM pads, the first portion adjacent the first surface of the redistribution substrate, and a second insulating film covering a second portion of the side surface of the plurality of UBM pads, the second portion above the first portion, the first portion is spaced apart from the first insulating film, and the second portion is in direct contact with the second insulating film.

2. The semiconductor package as claimed in claim 1, wherein a seed layer for the plurality of UBM pads is disposed only between the first portion of the side surface of the plurality of UBM pads and the first insulating film.

3. The semiconductor package as claimed in claim 2, wherein the seed layer for the plurality of UBM pads is not present between the second portion of the side surface of the plurality of UBM pads and the second insulating film.

4. The semiconductor package as claimed in claim 1, wherein the dummy pattern is disposed on the first insulating film, and has a side surface covered by the second insulating film.

5. The semiconductor package as claimed in claim 4, wherein the side surface of the dummy pattern is in direct contact with the second insulating film.

6. The semiconductor package as claimed in claim 4, wherein a seed layer for the dummy pattern is disposed only between the lower surface of the dummy pattern and the first insulating film.

7. The semiconductor package as claimed in claim 6, wherein the seed layer for the dummy pattern is not present between the side surface of the dummy pattern and the second insulating film.

8. The semiconductor package as claimed in claim 1, wherein the dummy pattern is spaced by a distance of 30 μm or less from an adjacent UBM pad, among the plurality of UBM pads.

9. The semiconductor package as claimed in claim 1, wherein the dummy pattern is spaced by a distance of 2 μm or more from the first surface of the redistribution substrate.

10. The semiconductor package as claimed in claim 1, wherein the plurality of UBM pads have respective thicknesses that are greater than a thickness of the redistribution layer connected thereto.

11. The semiconductor package as claimed in claim 1, wherein a portion of the UBM pads protrude from the first surface of the redistribution substrate.

12. The semiconductor package as claimed in claim 1, wherein the insulating member includes a photoimageable dielectric (PID) material.

13. The semiconductor package as claimed in claim 1, wherein: the plurality of redistribution layers include a redistribution via connecting redistribution layers disposed on adjacent levels, and the redistribution via has a shape narrowed in a direction of the first surface of the redistribution substrate from the second surface of the redistribution substrate.

14. The semiconductor package as claimed in claim 1, further comprising a molded portion disposed on the second surface of the redistribution substrate, and surrounding the at least one semiconductor chip.

15. The semiconductor package as claimed in claim 14, further comprising a heat dissipation member disposed on the at least one semiconductor chip and the molded portion.

16. A semiconductor package, comprising: a redistribution substrate having first and second surfaces, disposed opposite to each other, and including a plurality of insulating layers and a plurality of redistribution layers in the plurality of insulating layers, respectively, and electrically connected to each other; a plurality of under-bump metallurgy (UBM) pads disposed in the plurality of insulating layers and electrically connected to the plurality of redistribution layers, the plurality of UBM pads having lower surfaces exposed to the first surface of the redistribution substrate; a dummy pattern disposed between the plurality of UBM pads in the plurality of insulating layers, the dummy pattern having a lower surface located on a level higher than the lower surfaces of the plurality of UBM pads; and at least one semiconductor chip disposed on the second surface of the redistribution substrate and electrically connected to the plurality of redistribution layers, wherein: the lower surface of the dummy pattern is spaced apart from the plurality of insulating layers by a seed layer for the dummy pattern, and a side surface of the dummy pattern is in direct contact with an insulating film.

17. The semiconductor package as claimed in claim 16, wherein the seed layer for the dummy pattern is not present between the side surface of the dummy pattern and the insulating film.

18. A semiconductor package, comprising: a redistribution substrate having first and second surfaces, disposed opposite to each other, and including a plurality of insulating layers and a plurality of redistribution layers in the plurality of insulating layers, respectively, and electrically connected to each other; a plurality of under-bump metallurgy (UBM) pads disposed in the plurality of insulating layers and electrically connected to the plurality of redistribution layers, the plurality of UBM pads having lower surfaces exposed to the first surface of the redistribution substrate; a dummy pattern disposed between the plurality of UBM pads in the plurality of insulating layers, the dummy pattern having a lower surface located on a level higher than the lower surfaces of the plurality of UBM pads; at least one semiconductor chip disposed on the second surface of the redistribution substrate and electrically connected to the plurality of redistribution layers; and first seed layers for the plurality of UBM pads extending along side surfaces of the plurality of UBM pads, wherein a first extended length of each of the first seed layers is shorter than a length of the respective side surfaces of the plurality of UBM pads.

19. The semiconductor package as claimed in claim 18, further comprising second seed layers for the dummy pattern extended along the lower surface of the dummy pattern.

20. The semiconductor package as claimed in claim 19, wherein a second extended length of each of the second seed layers is substantially equal to a length of the lower surface of the dummy pattern.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0010] Features will become apparent to those of skill in the art by describing in detail example embodiments with reference to the attached drawings in which:

[0011] FIG. 1 is a cross-sectional view illustrating a semiconductor package according to an example embodiment;

[0012] FIG. 2 is a plan view of the semiconductor package illustrated in FIG. 1 taken along line I-I′;

[0013] FIG. 3 is an enlarged cross-sectional view of a portion “A1” of the semiconductor package shown in FIG. 1;

[0014] FIG. 4 is a plan view of a connection pad level along line II1-II1′ of the “A1” portion of the semiconductor package shown in FIG. 3;

[0015] FIG. 5 is a plan view of a connection pad along line II2-II2′ of the “A1” portion of the semiconductor package shown in FIG. 3;

[0016] FIG. 6 is a schematic view for explaining a cause of the undulation and an improvement method;

[0017] FIG. 7 is a graph comparing a thickness variation (undulation) of a cover insulating layer according to the thickness and the distance of the pattern;

[0018] FIGS. 8A to 8G are cross-sectional views of stages in a method of manufacturing a redistribution substrate according to an example embodiment;

[0019] FIGS. 9A to 9C are cross-sectional views of stages in a method of manufacturing a semiconductor package according to an example embodiment;

[0020] FIGS. 10A to 10D are cross-sectional views of stages in a method of manufacturing a redistribution substrate according to an example embodiment;

[0021] FIG. 11 is a cross-sectional view illustrating a semiconductor package according to an example embodiment;

[0022] FIG. 12 is a cross-sectional view illustrating a semiconductor package according to an example embodiment;

[0023] FIG. 13 is an upper plan view of the semiconductor package illustrated in FIG. 12;

[0024] FIG. 14 is an enlarged cross-sectional view of a portion “A2” of the semiconductor package illustrated in FIG. 12; and

[0025] FIG. 15 is a block diagram illustrating a configuration of a semiconductor package according to an example embodiment.

DETAILED DESCRIPTION

[0026] FIG. 1 is a cross-sectional view illustrating a semiconductor package according to an example embodiment, and FIG. 2 is a plan view of the semiconductor package illustrated in FIG. 1 taken along line I-I′.

[0027] Referring to FIGS. 1 and 2, a semiconductor package 100 according to the present example embodiment includes a redistribution substrate 130 having a first surface 130A and a second surface 130B opposite to each other, under-bump metallurgy (UBM) pads disposed on the first surface 130A of the redistribution substrate 130, and a semiconductor chip 150 disposed on the second surface 130B of the redistribution substrate 130.

[0028] The semiconductor chip 150 may include a semiconductor substrate having an active surface on which various individual elements are formed, and an inactive surface opposite to the active surface. The semiconductor substrate may include a single element semiconductor formed of a material such as silicon (Si) or germanium (Ge) or a compound semiconductor formed of a material such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs) or indium phosphide (InP). In an example embodiment, the semiconductor substrate may have a silicon on insulator (SOI) structure. For example, the semiconductor substrate constituting the semiconductor chip 150 may include a buried oxide (BOX) layer. The various individual devices may include, e.g., metal-oxide-semiconductor field effect transistors (MOSFETs) such as complementary metal-insulator-semiconductor (CMOS) transistors and/or an image sensor such as a system large scale integration (LSI) or CMOS imaging sensors (CIS).

[0029] The semiconductor chip 150 may include a plurality of contact pads 150P electrically connected to the individual elements and disposed on the active surface. The semiconductor chip 150 may be a memory chip or a logic chip. For example, the memory chip may be a volatile memory chip such as a dynamic random access memory (DRAM) (e.g., high bandwidth memory (HBM)) or a static random access memory (SRAM), or a phase-change random access memory (PRAM), or a nonvolatile memory chip such as a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FeRAM), or a resistive random access memory (RRAM). In addition, the logic chip may be, e.g., a microprocessor, an analog device, or a digital signal processor.

[0030] As shown in FIG. 1, the redistribution substrate 130 includes an insulating member 110 and a redistribution structure 120 disposed on different levels from the insulating member 110. The insulating member 110 includes a plurality of insulating layers 111, 112, 113, and 114, and the redistribution structure 120 includes a plurality of redistribution layers 121, 122, and 123 disposed at interfaces of the plurality of insulating layers 111, 112, 113, and 114, respectively. The redistribution substrate 130 may be used as an interposer for packaging the semiconductor chip 150 to be mounted on the main board.

[0031] An interface of the plurality of insulating layers 111, 112, 113, 114 defines a location of formation of the redistribution layers 121, 122, and 123, but in a final structure according to an example embodiment (e.g., when the plurality of insulating layers 111, 112, 113, and 114 are formed of the same material), an interface of the insulating layers 111, 112, 113, and 114 may not be directly observed visually. A portion of the plurality of redistribution layers 121, 122, and 123 may include redistribution vias 121V, 122V, and 123V connecting the redistribution layers 121, 122, and 123 disposed at adjacent levels. The redistribution vias 121V, 122V, and 123V have lower widths smaller than the upper widths according to the forming direction. For example, the redistribution vias 121V, 122V, and 123V may have a shape narrowed in a direction from the second surface 130B toward the first surface 130A.

[0032] The plurality of insulating layers 111, 112, 113, and 114 may include a resin such as, e.g., epoxy or polyimide. In an example embodiment, the plurality of insulating layers 111, 112, 113, and 114 may be formed of a photoimageable insulating material (PID). The plurality of redistribution layers 121, 122, and 123 may include, e.g., copper, nickel, stainless steel, or beryllium copper or other copper alloy.

[0033] The semiconductor chip 150 disposed on the second surface 130B of the redistribution substrate 130 may have a plurality of contact pads 150P electrically connected to the redistribution layer 123 adjacent to the second surface among the plurality of redistribution layers 121, 122, and 123. The redistribution substrate 130 may include a plurality of bonding pads 125 connected to the redistribution layer 123 and disposed on the second surface 130B. The plurality of bonding pads 125 may have a via portion 125V penetrating a portion of the insulating member 110 (that is, the insulating layer 114), respectively, and connected to the redistribution layer 123 adjacent to the second surface 130B. The via portion 125V of bonding pad 125 may have a lower end width that is less than an upper end width, similar to redistribution vias 121V, 122V, 123V. For example, the via portion 125V may have a shape narrowed in a direction from the second surface 130B toward the first surface 130A. The bonding pad 125 may include, e.g., copper, nickel, stainless steel or beryllium copper or other copper alloy, similar to the redistribution layers 121, 122, and 123.

[0034] The semiconductor chip 150 may be mounted on the second surface 130B of the redistribution substrate 130. The contact pads 150P of the semiconductor chip 150 may be respectively connected to the bonding pad 125 using connection bumps SB such as solder, respectively. The semiconductor chip 150 may be electrically connected to the redistribution structure 120. The semiconductor package 100 may further include an underfill resin 161 disposed between the active surface of the semiconductor chip 150 and the second surface 130B of the redistribution substrate 130. The underfill resin 161 may be formed to surround side surfaces of the connection bumps SB. The underfill resin 161 may include, e.g., an epoxy resin.

[0035] An upper surface 150T of the semiconductor chip 150 may be exposed through an upper surface of the molding portion 165, and heat may be easily released through the exposed upper surfaces of the semiconductor chip 150. The upper surface 150T of the semiconductor chip 150 may be obtained by grinding the upper surface of the molding portion 165. The upper surface 150T of the semiconductor chip 150 may have a coplanar surface that is substantially flat with the upper surface of the molding portion 165. The molding portion 165 may be made of, e.g., a hydrocarbon cyclic compound containing a filler. The filler may be, e.g., an SiO.sub.2 filler. In an example embodiment, the molding portion 165 may be formed of Ajinomoto Build-up Film (ABF).

[0036] The UBM pads 140 may be disposed on the insulating layer 111 that is a lowermost portion of the insulating member 110, and may be connected to the redistribution layer 121 adjacent to the first surface 130A of the plurality of redistribution layers 121, 122, and 123. At least one surface, e.g., a lower surface of the UBM pads 140, may be exposed to the first surface of the redistribution substrate 130. External connection conductors 180 may be disposed on the exposed lower surface, respectively. An external connection conductor 180 may be attached on the UBM layer of the redistribution substrate 130. The external connection conductor 180 may be, e.g., solder balls or bumps. The external connection conductor 180 may electrically connect the semiconductor package 100 to an external device (e.g., a motherboard).

[0037] In the present example embodiment, a dummy pattern 145 may be disposed between the UBM pads 140 in the insulating member 110, e.g., in the lowermost insulating layer 111. A lower surface of the dummy pattern 145 may have a lower surface disposed on a level, higher than the lower surface of the UBM pads 140. The dummy pattern 145 may be disposed in the insulating member 110 (for example, the lowermost insulating layer 111) without being exposed to the outside of the insulating member 110.

[0038] Referring to FIG. 3, an arrangement of the UBM pad and the dummy pattern employed in the present example embodiment will be described in detail.

[0039] FIG. 3 is an enlarged cross-sectional view of portion “A1” of the semiconductor package shown in FIG. 1, and FIGS. 4 and 5 are plan views by cutting portions “A1” of the semiconductor package shown in FIG. 3 taken along the lines II1-II1′ and II2-II2′, respectively. Planes in FIGS. 4 and 5 may be understood as an area corresponding to “B” in an entire plane of the semiconductor package 100 shown in FIG. 2.

[0040] Referring to FIGS. 3 and 4, the dummy pattern 145 may be disposed between the UBM pads 140 to alleviate a cause of undulation of the redistribution layer 121 formed in a subsequent process. The dummy pattern 145 employed in the present example embodiment may be disposed in the lowermost insulating layer 111 on which the UBM pads 140 are disposed.

[0041] The undulation refers to an upper surface level variation of the cover insulating layer I that covers a conductor pattern P formed on the substrate S as illustrated in FIG. 6, that is, a thickness variation (Δt) of the cover insulating layer I. When the thickness variation (Δt) is large, a failure (e.g., short) of a redistribution layer (not shown) to be formed on the cover insulating layer may be caused.

[0042] An undulation may occur during a curing shrinkage process of the insulating layer I. Thus, the undulation may become more serious as a shrinkage ratio increases. The shrinkage ratio may be determined by a volume of the cover insulation layer I when the same material is used (under conditions in which the shrinkage ratio of the material is the same), specifically, it may be determined by a width Ws between the pattern P and a thickness of the pattern P.

[0043] FIG. 7 is a graph comparing a thickness variation (undulation) of a cover insulating layer according to the thickness and the distance of the pattern. Referring to FIG. 7, the thickness deviation Δt decreases as the thickness (tp) of the pattern P decreases and as the width (Ws) between the patterns P decreases.

[0044] Referring to FIG. 7, the thickness deviation Δt decreases as the thickness (tp) of the pattern P decreases and as the width (Ws) between the patterns P decreases. For example, the thickness tc of the redistribution layer 121 may be about 5 μm or less (e.g., about 2 μm to about 4 μm), whereas the thickness (ta) of the UBM pads 140 is about 8 μm or more. Therefore, since the UBM pads 140 are not only disposed at a lowermost portion, but also have a relatively large thickness (ta), the UBM pads 140 serve as a major cause of undulation.

[0045] Meanwhile, since the UBM pads 140 should be in contact with external connection conductors 180 for connecting external circuits (e.g., a main board), the UBM pads 140 may be arranged at sufficient distances D. For example, the distance D of the UBM pads 140 may be at least about 50 μm, in some example embodiments, the distance D of the UBM pads 140 may be at least about 100 μm.

[0046] Referring to FIG. 6, e.g., when the distance D between the UBM pads 140 is about 50 μm or more and the thickness of the lowermost insulating layer 111 is about 11 μm, the undulation may occur seriously at about 3 μm or more. To prevent this, the dummy pattern 145 is disposed between the UBM pads 140.

[0047] According to the width W of the dummy pattern 145, the thickness of the insulating layer 111 is maintained between the patterns (e.g., the UBM pad 140 and the dummy pattern 145)), but the distance d may be largely reduced. As such, even if the thickness of the lowermost insulating layer 111 is large (e.g., about 11 μm), the distance d between the UBM pad 140 and the dummy pattern 145 is reduced, so that the undulation can be significantly reduced. For example, referring to FIG. 6, by reducing the distance d between the UBM pad 140 and the dummy pattern 145 to about 30 μm or less, an effect of reducing the undulation may be expected. In particular, when the distance d is about 20 μm or less, the thickness deviation Δt due to the undulation may be reduced to less than 2 μm.

[0048] In addition, the dummy pattern 145 may be disposed in the lowermost insulating layer 111 so as not to be exposed to the first surface 130A of the redistribution substrate 130. Thus, the lowermost insulating layer 111 associated with the UBM pad 140 may be formed by being divided into a first insulating film 111a and a second insulating film 111b. The first insulating film 111a protects the dummy pattern 145 from being exposed to the outside, and the thickness (t0) of the first insulating film 111a may be sufficient to ensure stable insulation. For example, the thickness t0 of the first insulating film 111a may be about 2 μm or more. The thickness t0 may define a level difference between the bottom surface of the UBM pad 140 and the bottom surface of the dummy pattern 145.

[0049] In the present example embodiment, the UBM pads 140 and the dummy pattern 145 may have a substantially flat upper surface, respectively. A thickness (tb) of the dummy pattern 145 may almost correspond to thicknesses (ta−t0), that is, excluding or subtracting the thickness (t0) of the first insulating film 111a from the thickness (ta) of the UBM pad 140. Such a structure may be formed by processes set forth below in connection with FIGS. 8A to 8G according to an example embodiment (in contrast to the processes set forth below in connection with FIGS. 10A to 10D according to another example embodiment).

[0050] The UBM pad employed in the present example embodiment includes a planar conductive pattern, and may be connected by a redistribution via 121V of the redistribution layer 121 penetrating the lowermost insulating layer 111 (for example, a second insulating film 111b).

[0051] In the present example embodiment, a redistribution layer 121 that is closest to the first surface 130A of the plurality of redistribution layers 121, 122, and 123 (that is, a redistribution layer 121 directly connected to the plurality of UBM pads) may be provided to connection pads having the same shape as the plurality of UBM pads 140 to correspond to the plurality of UBM pads 140, respectively, as illustrated in FIG. 5. In addition, an additional dummy pattern 121D may be disposed between the connection pads, and the additional dummy pattern 121D may also have a shape and an area that are substantially the same as the dummy pattern disposed between the UBM pads 140. In another example embodiment, the redistribution layer 121 closest to the first surface 130A may be a portion of a general redistribution structure, such as a line pattern, instead of connection pads.

[0052] FIGS. 8A to 8G are cross-sectional views of stages in a method of manufacturing a redistribution substrate according to an example embodiment.

[0053] The present example embodiment may be used to manufacture the redistribution substrate of the semiconductor package of FIG. 1, and may be understood as a process diagram of an “A1” portion of FIG. 1, that is, a portion corresponding to FIG. 3.

[0054] Referring to FIG. 8A, a first insulating film having a plurality of first openings may be formed.

[0055] A carrier 210 may be provided as a substrate for building up the redistribution structure. A first insulating film 111a may be formed on the carrier 210, and a plurality of first openings O1 for UBM pads (for example, a lower region of the UBM pads) may be formed in the first insulating film 111a. In the present example embodiment, a formation process of the UBM pad may use a plating process twice. The first opening O1 of the first insulating film 111a may define a lower region of the UBM pad, and the first insulating film 111a may be formed to have a thickness (t0) that is less than a desired thickness of the UBM pad (ta of FIG. 3). The first insulating film 111a may include a resin such as epoxy or polyimide. For example, the first insulating film 111a may include a photosensitive insulating material PD. When PID is used as the first insulating film 111a, the first opening O1 may be formed using a photolithography process.

[0056] Referring to FIG. 8B, a first photoresist film PR1 having openings O2′ overlapping the plurality of first openings O1, respectively, may be formed on the first insulating film 111a.

[0057] Before forming the first photoresist film PR1, a first seed layer S1 for the plating process may be formed on an upper surface of the first insulating film 111a and surfaces exposed to the first opening O1. For example, the first seed layer S1 may include a Ti/Cu layer. In the first photoresist film PR1, overlapping openings O2′ opening a first plating region for the UBM pad may be formed by using a photolithography process. The overlapping openings O2′ may be arranged to overlap the first opening O1.

[0058] Referring to FIG. 8C, first metal patterns 140a may be formed in the plurality of first openings O1, respectively.

[0059] The first metal pattern 140a (also referred to as a ‘lower region of the UBM pad’) may be formed by a plating process using the first photoresist film PR1 and the first seed layer S1. The first metal pattern 140a may include, e.g., copper. The present plating process may be a primary plating process for the UBM pad. In the present plating process, at least a portion of the plurality of first openings O1 may be filled by the first metal pattern 140a, while at least a portion of the overlapping opening O2′ may not be filled. The present plating process may be performed by, e.g., immersion plating, electroless plating or electroplating.

[0060] Referring to FIG. 8D, after removing the first photoresist film PR1, a second photoresist film PR2 having a plurality of second openings O2 (openings for the plurality of first metal patterns 140a) and a third opening O3 between the second openings O2 may be formed on the first insulating film 111a.

[0061] The second photoresist film PR2 may be formed on the first insulating film 111a, on which a plurality of first metal patterns 140a are formed and from which the first photoresist film PR1 is removed. The plurality of second openings O2 (opening the plurality of first metal patterns 140a, respectively) and a third opening O3 between the plurality of second openings O2 may be formed in the second photoresist film PR2 using a photolithography process. The second openings O2 may have a size corresponding to the first openings O1. The third opening O3 may define a region for forming a dummy pattern (145 of FIG. 3), and some regions of the first seed layer S1 disposed on the first insulating film 111a may be opened through the third opening O3.

[0062] Referring to FIG. 8E, second metal patterns 140b and 145 may be formed in the plurality of second openings O2 and the third openings O3, respectively.

[0063] The second metal patterns 140b and 145 may be formed by a plating process using the second photoresist film PR2. In the present plating process, not only the region of the seed layer S1 exposed by the third opening O3, but also the first metal pattern 140a formed in advance may operate as a seed. The present plating process may be a secondary plating process for forming an upper region (corresponding to ‘140b’ among the second metal patterns) of the UBM pad. In the present secondary plating process, a dummy pattern (corresponding to 145 among the second metal patterns) may be formed in the third opening O3. The present plating process may be performed by, e.g., immersion plating, electroless plating or electroplating, similarly to the primary plating process.

[0064] Referring to FIG. 8F, the second photoresist film PR2 may be removed, and a second insulating film 111b may be formed on the first insulating film 111a to cover the second metal patterns 140b and 145.

[0065] The second insulating film 111b may be provided as a lowermost insulating layer 111 related to the UBM pad 140 together with the first insulating film 111a. For example, the second insulating film 111b may be a PID material similar to the first insulating film 111a. The first metal patterns 140a of the plurality of first openings O1 and the second metal patterns 140b of the plurality of second openings O2 may be provided as the plurality of UBM pads 140, and the second metal patterns 145 of the third opening O3 may be provided as the dummy pattern 145.

[0066] Referring to FIG. 8G, a redistribution layer 121 connected to the UBM pad 140 may be formed on the second insulating film 111b.

[0067] When the second insulating film 111b is PID, the redistribution layer 121 connected to the UBM pad 140 may be formed using a photolithography process and a plating process. For example, a hole connected to the UBM pad 140 may be formed for a photolithography process, a redistribution via 121V may be formed in the hole using a plating process, and a redistribution layer 121 connected to the redistribution via 121V may be formed in the second insulating film 111b.

[0068] When the second insulating film 111b is not PID, a process of forming the hole in the second insulating film 111b may be formed by, e.g., a laser drilling method using a UV laser or an Excimer laser.

[0069] As shown in FIG. 8G, a second seed layer S2 for the plating process may remain in the redistribution layer 121 along a surface in contact with the second insulating film 111b. In the present example embodiment, the first seed layer S1 may not be disposed on the surface of the upper region 140b of the UBM pad 140, but may be disposed only on the surface of the lower region 140a of the UBM pad 140. Thus, the first seed layer S1 for the UBM pad 140 according to the present example embodiment may be disposed between the plurality of UBM pads 140 and the first insulating film 111a, but the first seed layer S1 may not be present between the plurality of UBM pads 140 and the second insulating film 111b.

[0070] In addition, a portion of the first seed layer S1 for the dummy pattern 145 may be disposed between the dummy pattern 145 and the first insulating film 111a, but may not be present between the dummy pattern 145 and the second insulating film 111b.

[0071] The redistribution substrate 130 illustrated in FIG. 9A may be formed by repeatedly performing the formation process of the insulating layers 112, 113, and 114, and the redistribution layers 122, 123, and 125, described above (the process of FIG. 8G).

[0072] In the process illustrated in FIG. 8G, the first and second photoresist films PR1 and PR2 used in each plating process are illustrated as using a negative-type photoresist. Thus, the first photoresist film PR1 may be cured at a time of exposure, and the first photoresist film PR1 may be peeled off and removed for an additional plating process (see, FIG. 8E) after the primary plating process (see, FIG. 8C), and the second photoresist film PR2 may be formed. In another example embodiment, when a positive-type photoresist is used as the first photoresist film PR1, only the exposed portion is developed, so that the first photoresist PR1 may not be peeled off, and an exposure/development process may be applied to the first photoresist PR1 to directly form the third opening (O3 of FIG. 8D).

[0073] FIGS. 9A to 9C are cross-sectional views of stages in a method of manufacturing a semiconductor package according to an example embodiment.

[0074] The redistribution substrate 130 illustrated in FIG. 9A may be a redistribution substrate manufactured by the process illustrated in FIGS. 8A to 8G.

[0075] A plurality of bonding pads 125 connected to the redistribution layer 123 may be formed on the second surface of the redistribution substrate 130. Thereby, the semiconductor chip 150 may be electrically connected to the redistribution structure 120. A formation process of the bonding pad 125 may also be similar to a formation process of the redistribution layer. The bonding pad 125 may be connected to a redistribution layer 123 adjacent to the second surface 130B by a via portion 125V penetrating through an uppermost insulating layer 114.

[0076] Next, referring to FIG. 9B, a semiconductor chip 150 may be mounted on the second surface 130B of the redistribution substrate 130.

[0077] In the present process, contact pads 150P of the semiconductor chip 150 may be connected to bonding pads 125 disposed on the second surface 130B of the redistribution substrate 130 by connection bumps SB. An underfill resin 161 may be charged between the semiconductor chip 150 and the redistribution substrate 130. The underfill resin 161 may be formed to surround the side surface of the connection bump SB. The underfill resin 161 may include, e.g., an epoxy resin.

[0078] Next, referring to FIG. 9C, a molding portion 165 protecting the semiconductor chip 150 may be formed, and the upper surface of the semiconductor chip 150 may be exposed from the upper surface of the molding portion 165 using a grinding process.

[0079] For example, the molding portion 165 may be formed to cover the semiconductor chip 150 disposed on the redistribution substrate 130, and the upper surface of the molding portion 165 may be ground to expose the upper surface of the semiconductor chip 150 (a dashed line indicates a portion that is removed by a grinding process). Through the grinding process, an upper surface 150T of the semiconductor chip 150 may be exposed to improve heat dissipation and reduce the thickness of the semiconductor package. The upper surface of the semiconductor chip 150 may have a flat surface that is substantially coplanar with the upper surface of the molding portion 165. The molding portion 165 may include, e.g., an ABF.

[0080] The manufacturing method of the redistribution substrate illustrated in FIGS. 8A to 8G may include a formation process of a UBM pad using a plating process twice, but the UBM pad may be formed together with a dummy pattern in a single plating process.

[0081] FIGS. 10A to 10D are cross-sectional views of stages in a method of manufacturing a redistribution substrate according to an example embodiment.

[0082] Referring to FIG. 10A, a first insulating film 111a having a plurality of first openings O1 may be formed. A photoresist film having a plurality of second openings O2 overlapping the plurality of first openings O1, respectively, and a dummy pattern opening Od disposed between the plurality of second openings O2, may be formed on the first insulating film 111a.

[0083] The plurality of overlapping first and second openings O1 and O2 may provide a plurality of UBM openings Op, respectively. Unlike the first photoresist film (PR1 of FIG. 8B) of the example embodiment described above, the photoresist film PR employed in the present example embodiment forms an opening Od for dummy pattern together with the second opening O2 before applying the plating process (that is, a primary plating process).

[0084] The depth h1 of the plurality of UBM openings Op corresponds to the sum of the thickness of the first insulating film 111a and the thickness of the photoresist film PR. The dummy pattern opening Od corresponds to the thickness of a photoresist film PR. The plurality of UBM openings Op may have a depth h1 greater than the depth h2 of the dummy pattern opening Od.

[0085] Next, referring to FIG. 10B, a plurality of UBM pads 140′ and a dummy pattern 145′ may be formed in the plurality of UBM openings Op and the dummy pattern openings Od, respectively.

[0086] The plurality of UBM pads 140 and the dummy pattern 145 may be formed using a plating process. In the present example embodiment, the dummy pattern 145′ may be formed together with the UBM pad 140′ using a single plating process. The present plating process may be performed by using the seed layer S1 regions exposed in the plurality of UBM openings Op and the dummy pattern openings Od, respectively.

[0087] As described above, a depth h1 of the plurality of UBM openings Op may be greater than a depth h2 of the dummy pattern openings Od. Therefore, when the plurality of UBM pads 140 ‘and the dummy pattern 145’ are formed at the same time by using one plating process, there may be a slight height deviation. As shown in FIG. 10B, the plurality of UBM pads 140′ may have a concave upper surface 140T ‘ if the plurality of UBM openings Op is not sufficiently filled. In contrast, the dummy pattern 145’ may have a convex upper surface 145T′ if the dummy pattern opening Od is slightly overfilled.

[0088] Referring to FIG. 10C, the photoresist film PR may be removed, and a second insulating film 111b may be formed on the first insulating film 111a to cover the plurality of UBM pads 140′ and the dummy pattern 145′.

[0089] The second insulating film 111b may be provided as the lowermost insulating layer 111 associated with the UBM pad 140 together with the first insulating film 111a. For example, the second insulating film 111b may be a PID material similar to the first insulating film 111a. For example, the second insulating film 111b may be a PID material similar to the first insulating film 111a.

[0090] Referring to FIG. 10D, a redistribution layer 121 connected to the UBM pad 140′ may be formed on the second insulating film 111b.

[0091] When the second insulating film 111b is PID, the redistribution layer 121 connected to the UBM pad 140 may be formed using a photolithography process and a plating process. For example, a hole connected to the UBM pad 140′ may be formed for a photolithography process, a redistribution via 121V may be formed in the hole using a plating process, and a redistribution layer 121 connected to the redistribution via 121V may be formed in the second insulating film 111b.

[0092] In the present example embodiment, similar to the previous example embodiment, a second seed layer S2 may remain in the redistribution layer 121 along a surface in contact with the second insulating film 111b. A first seed layer S1 for the UBM pad 140 may be disposed between the plurality of UBM pads 140 ‘and the first insulating film 111a, but may not be present between the plurality of UBM pads 140’ and the second insulating film 111b.

[0093] In addition, a portion of the first seed layer S1 for the dummy pattern 145′ may be disposed between the dummy pattern 145′ and the first insulating film 111a, but may not be present between the dummy pattern 145′ and the second insulating film 111b.

[0094] The redistribution substrate 130 illustrated in FIG. 9A may be formed by repeatedly performing a formation process of the insulating layers 112, 113, and 114 and the redistribution layers 122, 123, and 125 described above.

[0095] FIG. 11 is a cross-sectional view illustrating a semiconductor package according to an example embodiment. The semiconductor package illustrated in FIG. 11 may include a redistribution substrate manufactured by the process illustrated in FIGS. 10A to 10D.

[0096] The structure illustrated in FIG. 11 may be the structures illustrated in FIGS. 1 to 3, except that in the semiconductor package 100A according to the present example embodiment, the UBM pad 140′ and the dummy pattern 145′ have a concave upper surface 140T′ and a convex upper surface 145T′, respectively, and some lower regions 140e of the UBM pad 140′ are exposed. Accordingly, the description of the example embodiment shown in FIGS. 1 to 3 may be combined with the description of the present example embodiment unless otherwise stated.

[0097] The UBM pad 140′ and the dummy pattern 145′ in the present example embodiment may have a concave upper surface 140T ‘and a convex upper surface 145T’, respectively. As described in the foregoing process (see, FIG. 10B), the plurality of UBM pads 140′ may have a concave upper surface 140T′ if the plurality of UBM openings Op are not sufficiently filled, whereas the dummy pattern 145′ may have a convex upper surface 145T′ if the opening Od for dummy pattern is somewhat overfilled.

[0098] A de-scum or etching process using plasma or the like, may be performed on the first surface 130A of the redistribution substrate 130, and the lowermost insulating layer 111 may be partially etched, such that some lower regions 140e of the UBM pad 140′ may be exposed. The exposed lower region 140e of the UBM pad 140 may ensure stable connection with the external connection conductor 180.

[0099] FIG. 12 is a cross-sectional view illustrating a semiconductor package according to an example embodiment, FIG. 13 is an upper plan view of the semiconductor package illustrated in FIG. 12, and FIG. 14 is an enlarged cross-sectional view of a portion “A2” of the semiconductor package illustrated in FIG. 12.

[0100] The structures illustrated in FIGS. 12 and 13 may be similar to the structures shown in FIGS. 1 to 3, except that a second dummy pattern 145b for reducing undulation is introduced into some redistribution layers 121, and a plurality of semiconductor chips 150A and 150B and a heat sink 195 are included. Accordingly, the description of the example embodiment shown in FIGS. 1 to 3 may be combined with the description of the present example embodiment unless otherwise stated.

[0101] Similar to the dummy pattern 145 of the above-described example embodiment, a first dummy pattern 145a may be disposed between the plurality of UBM pads 140 in the insulating layer 111 to reduce undulation from the UBM pads 140. The first dummy pattern 145a may be spaced apart from the first surface 130A of the redistribution substrate 130, and may have a thickness smaller than that of the plurality of UBM pads 140. For example, the first dummy pattern 145a may be disposed between the first and second insulating films 111a and 111b of the lowermost insulating layer 111.

[0102] Referring to FIG. 14, a second dummy pattern 145b may be disposed on a level that is higher than a level of the plurality of redistribution layers 121 and between the plurality of redistribution layers 121. The second dummy pattern 145b may be spaced apart from the first surface 130A of the redistribution substrate 130, and may have a thickness smaller than the thickness of the redistribution layer 121. For example, the second dummy pattern 145b may be disposed between the first and second insulating films 112a and 112b of the insulating layer 112. When the redistribution layer 121 has a relatively larger thickness than the other redistribution layers or a distance between the redistribution layers 121 is large, the second dummy pattern 145b may be disposed to reduce the distance.

[0103] In the present example embodiment, first and second semiconductor chips 150A and 150B may be mounted on the second surface 130B of the redistribution substrate 130. The contact pad 150P of the first and second semiconductor chips 150A and 150B may be connected to the bonding pad 125 by connection bumps, respectively. A molding portion 165 may be formed to surround some or all of the first and second semiconductor chips 150A and 150B. The molding portion 165 may include, e.g., an epoxy molding compound. Similar to the previous example embodiment, the molding portion 165 may have a flat upper surface that is coplanar with upper surfaces of the first and second semiconductor chips 150A and 150B.

[0104] The semiconductor package 100B according to the present example embodiment may further include a heat conductive material layer 191 and a heat sink 195 sequentially disposed on the upper surfaces of the first and second semiconductor chips 150A and 150B. The heat conductive material layer 191 may be disposed between the heat sink 195, the first and second semiconductor chips 150A and 150B, and the molding portion 165. The heat conductive material layer 191 may help smoothly discharge heat, generated by the first and second semiconductor chips 150A and 150B, to the heat sink 195. The heat conductive material layer 191 may be made of, e.g., a thermal interface material (TIM).

[0105] The heat conductive material layer 191 may be made of, e.g., an electrically insulating material, or may be made of a material capable of maintaining electrical insulation including an insulating material. The heat conductive material 191 may include, e.g., an epoxy resin. Specific examples of the heat conductive material layer 191 may include mineral oil, grease, gap filler putty, phase change gel, phase change material pad pads, or particle filled epoxy.

[0106] The heat sink 195 may be disposed on the heat conductive material layer 191. The heat sink 195 may be, e.g., a heat sink, a heat spreader, a heat pipe, or a liquid cooled cold plate.

[0107] FIG. 15 is a block diagram illustrating a configuration of a semiconductor package according to an example embodiment.

[0108] Referring to FIG. 15, the semiconductor package 1000 may include a micro processing unit 1010, a memory 1020, an interface 1030, a graphic processing unit 1040, functional blocks 1050, and a bus 1060 connecting thereto. The semiconductor package 1000 may include both the micro processing unit 1010 and the graphic processing unit 1040, or may include only one of the two.

[0109] The micro processing unit 1010 may include a core and an L2 cache. For example, the micro processing unit 1010 may include a multi-core. Each core of a multi-core may have the same or different performance. In addition, each core of the multi-core may be activated at the same time, or may be different from each other when activated.

[0110] The memory 1020 may store a result processed in the functional blocks 1050, and the like, under a control of the micro processing unit 1010. The interface 1030 may exchange information or signals with external devices. The graphic processing unit 1040 may perform graphic functions. For example, the graphic processing unit 1040 may perform a video codec or process 3D graphics. The functional blocks 1050 may perform various functions. For example, when the semiconductor package 1000 is an application processor (AP) used in a mobile device, some of the functional blocks 1050 may perform a communication function. In this case, the semiconductor package 1000 may include the semiconductor package 100B described with reference to FIG. 12.

[0111] By way of summation and review, a semiconductor package may be manufactured by forming a redistribution substrate (e.g., an interposer) having a redistribution layer, and mounting and molding a semiconductor chip on the redistribution substrate. The redistribution substrate may be formed by repeatedly performing a formation process of an insulating layer and a pattern of each layer (e.g., UBM pads and a plurality of redistribution layers) on each insulating layer.

[0112] As described above, embodiments may provide a semiconductor package having high reliability by improving undulation generated in a redistribution substrate. Embodiments may provide a method of manufacturing a semiconductor package having high reliability by reducing undulation in a redistribution substrate.

[0113] As described above, by introducing a dummy pattern that is not exposed to the outside between under bump metal (UBM) pads, undulation generated in a redistribution layer formed in a subsequent process may be reduced and reliability of a semiconductor package may be improved. In addition to the UBM pads, a dummy pattern may be disposed between the redistribution layers in a thinner layer than the redistribution layer to reduce undulation.

[0114] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. In some instances, as would be apparent to one of ordinary skill in the art as of the filing of the present application, features, characteristics, and/or elements described in connection with a particular embodiment may be used singly or in combination with features, characteristics, and/or elements described in connection with other embodiments unless otherwise specifically indicated. Accordingly, it will be understood by those of skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims.