A semiconductor package includes a leadframe including leads and a die attach pad (DAP) inside the leads, and at least one semiconductor die having a top side including circuitry electrically connected to bond pads and a bottom side attached to a bottom side portion of the DAP. The package includes a mold compound and a heat slug having a top side and a bottom side positioned within a cavity defined by sidewalls of the mold compound. The heat slug has an area greater than an area of the DAP is attached by its bottom side with a thermally conductive adhesive material to a top side portion of the DAP. Bondwires are between the leads and the bond pads. Exposed from the mold compound is a bottom side surfaces of the leads and the top side of the heat slug.

A semiconductor package including a substrate; a semiconductor stack on the substrate; an underfill between the substrate and the semiconductor stack; an insulating layer conformally covering surfaces of the semiconductor stack and the underfill; a chimney on the semiconductor stack; and a molding member surrounding side surfaces of the chimney, wherein the semiconductor stack has a first upper surface that is a first distance from the substrate and a second upper surface that is a second distance from the substrate, the first distance being greater than the second distance, wherein the chimney includes a thermally conductive filler on the first and second upper surfaces of the semiconductor stack, the thermally conductive filler having a flat upper surface; a thermally conductive spacer on the thermally conductive filler; and a protective layer on the thermally conductive spacer, and wherein an upper surface of the thermally conductive spacer is exposed.

A module that improves heat-dissipation efficiency and can prevent a warp and a deformation of the module is provided. A module includes a substrate, a first component mounted on an upper surface of the substrate, a heat-dissipation member, and a sealing resin layer that seals the first component and the heat-dissipation member. The heat-dissipation member is formed to be larger than the area of the first component when viewed in a direction perpendicular to the upper surface of the substrate and prevents heat generation of the module by causing the heat generated from the first component to move outside the module. The heat-dissipation member has through holes, and the through holes are packed with a resin, which can prevent the sealing resin layer from peeling off.

A method may include coating an electronic module in a tool, where the electronic module has a first sub-module and a second sub-module, where the tool has a first tool part and a second tool part, where the tool has a cavity at least partially formed between the first tool part and the second tool part, and where the first sub-module and the second sub-module are supported on the tool and held in the cavity at a spatially defined distance relative to one another in a contactless manner during the coating process. A tool for performing such method may include a first tool part and a second tool part that form a cavity, where the first tool part has a first molding surface section and at least one first supporting section that extends over the first molding surface section and the second tool part has a second molding surface section and at least one second supporting section that extends over the second molding surface section.

A semiconductor device includes: a metal block; a semiconductor element fixed to an upper surface of the block with a first joining material; a main terminal fixed to an upper surface of the element with a second joining material; a signal terminal electrically connected to the element; and a mold resin covers the element, the first and second joining materials, a part of the block, of the main and signal terminals. In the element, a current flows in a longitudinal direction. A lower surface of the block is exposed from the resin. The main and the signal terminals are exposed from a side surface of the resin. The main terminal has a first portion in the resin, a second portion continuous with the first portion and bent downward outside the resin, and a third portion continuous with the second portion and substantially parallel to a lower surface of the resin.

A semiconductor device with high heat dissipation efficiency includes a base structure, a semiconductor chip, a heat dissipating structure, and a package body. The semiconductor chip is disposed on the base structure and has a first surface distant from the base structure. The heat dissipating structure includes a buffer layer and a first heat spreader. The buffer layer is disposed on the first surface of the semiconductor chip and a coverage rate thereof on the first surface is at least 10%. The first heat spreader is disposed on the buffer layer and bonded to the first surface of the semiconductor chip through the buffer layer. The package body encloses the semiconductor chip and the heat dissipating structure, and the package body and the buffer layer have the same heat curing temperature.

Provided is a semiconductor package having a package housing in an engraved surface form and a method of manufacturing the same, wherein the semiconductor package includes: at least one substrate on which at least one semiconductor chip is installed; at least one terminal lead electrically connected to the substrates; electrical connectors for connecting the semiconductor chips to the substrates or the terminal leads; a package housing covering the semiconductor chips, the electrical connectors, and the at least one substrate; at least one stopper which is formed of a material same as that of the package housing, is higher by a certain height than exposed surfaces of the substrates, is disposed on the exposed surfaces of the substrates, or covers at least a part of the exposed surfaces; and at least one heat sink transmitting heat from the semiconductor chips and radiating heat, wherein the at least a part of the exposed surfaces of the at least one substrate is formed on the upper surface, the lower surface, or the upper and lower surfaces of the package housing and the exposed surfaces of the at least one substrate are joined to the heat sinks by using heat transfer connectors interposed therebetween. Accordingly, the full thickness of the heat transfer connectors may be uniformly maintained.

A semiconductor device module includes a device mounted on the surface of an organic substrate; a heat dissipation block bonded and fixed to the surfaces of the device; and a molded resin sealing the device with at least one surface of the heat dissipation block being exposed. The heat dissipation block includes a first portion and a second portion made of materials different in hardness: the first portion is harder than the second portion, and a gradient in hardness from the first portion on the side exposed from the molded resin to the second portion on the side bonded to the device, to keep a good grinding performance of grinding wheel.

A planar multi-chip device includes a base structure and a plurality of functional chips. The base structure has a central area and a peripheral area outside the central area. The central area includes a first conductive portion arranged therein. The peripheral area includes a plurality of second conductive portions and a plurality of third conductive portions arranged therein and separated from each other. The functional chips are arranged on the base structure, and each of the functional chips has a portion located on and electrically connected to the first conductive portion. At least two of the functional chips are configured to be in signal communication with each other via at least one of the third conductive portions.

A vertical type multi-chip device includes a base structure, an intermediate layer, a first functional chip, and a second functional chip. The intermediate layer is disposed on the base structure and has a first signal transmission path and a second signal transmission path. The first functional chip is embedded in the intermediate layer and electrically connected to the base structure. The second functional chip is disposed on the intermediate layer and configured to be electrically connected to the first functional chip via the first signal transmission path and to the base structure via the second signal transmission path.