The present disclosure provides a wafer level packaging method and a package structure. The wafer level packaging method includes: forming a bonding structure including a device wafer and a plurality of first chips bonded to the device wafer; conformally covering the plurality of first chips and the device wafer exposed by the plurality of first chips with an insulating layer; conformally covering the insulating layer with a shielding layer; and forming an encapsulation layer on the shielding layer. The wafer level package structure includes: a device wafer; a plurality of first chips bonded to the device wafer; an insulating layer conformally covering the plurality of first chips and the device wafer exposed by the plurality of first chips; a shielding layer conformally covering the insulating layer; and an encapsulation layer formed on the shielding layer. The wafer level package structure provides a reduced volume and a reduced thickness.

A module board and a memory module are provided. The module board includes a first branch line for connecting a clock signal terminal disposed on at least one surface to a first branch point; a first signal line for connecting the first branch point to a first module clock signal terminal; a second signal line for connecting the first module clock signal terminal to the k.sup.th module clock signal terminal and a first termination resistance terminal; a third signal line for connecting the first branch point to a (k+1).sup.th module clock signal terminal; and a fourth signal line for connecting the (k+1).sup.th module clock signal terminal to a 2k.sup.th module clock signal terminal and the second termination resistance terminal, wherein a length of the third signal line is greater than a sum of a length of the first signal line and a length of the second signal line.

A power electronics module includes a substrate with a substrate metallization layer, which is separated into conducting areas for providing conducting paths for the power electronics module; a semiconductor switch chip bonded with a first power electrode to a first conducting area of the substrate metallization layer; a conductor plate bonded to a second power electrode of the semiconductor switch chip opposite to the first power electrode.

A stacked-plate heat exchanger for cooling a plurality of heat-generating electronic components arranged in a plurality of layers comprises a stack of flat tubes defining a plurality of parallel fluid flow passages, the tubes being separated by spaces for receiving the electronic components. One or more flow-restricting ribs is arranged within at least some of the fluid flow passages to partially block fluid flow between at least one the manifolds and the heat transfer area by reducing the height of the fluid flow passage outside the heat transfer area, along at least a portion of the width of the fluid flow passage, in order to improve the flow distribution of a heat transfer fluid between and within the fluid flow passages of the heat exchanger, and to minimize bypass flow at the outer edges of the fluid flow passage.

Transistor packages in space-constrained applications are disclosed. An apparatus may comprise a first transistor package and a second transistor package, wherein the first transistor package is stacked upon the second transistor package. The apparatus may further comprise a cover coupled to a printed circuit board (PCB) that is configured to cover at least a portion of the stacked first and second transistor packages. The first and second transistor package may be components in a power circuit that is configured to down-convert a received voltage from a first voltage level to a second, lower voltage level.

In accordance with an embodiment, a method includes: monitoring a temperature difference between two double-side cooled (DSC) power modules of a plurality of DSC power modules arranged in stacks of DSC power modules; comparing the temperature difference with a first temperature threshold; detecting a cooling pipe system blockage when the temperature difference is above the first temperature threshold; and after detecting the cooling pipe system blockage, disabling gate driver circuits coupled to the plurality of DSC power modules or operating the DSC power modules in a low-power mode. Each stack includes a plurality of DSC power modules. Each DSC power module has a top surface and a bottom surface, which are each thermally coupled with one or more cooling channels of a cooling pipe system. The two DSC power modules are thermally coupled with a same cooling channel of the one or more cooling channels.

A semiconductor device includes first and second chips that are stacked such that first surfaces of their element layers face each other. Each chip has a substrate, an element layer on a first surface of the substrate, pads on the element layer, and vias that penetrate through the substrate and the element layer. Each via is exposed from a second surface of the substrate and directly connected to one of the pads. The vias include a first via of the first chip directly connected to a first pad of the first chip and a second via of the second chip directly connected to a second pad of the second chip. The pads further include a third pad of the second chip which is electrically connected to the second pad by a wiring in the element layer of the second chip and to the first pad through a micro-bump.

A semiconductor device includes an interposer disposed on a substrate. A first major surface of the interposer faces the substrate. A system on a chip is disposed on a second major surface of the interposer. The second major surface of the interposer opposes the first major surface of the interposer. A plurality of first passive devices is disposed in the first major surface of the interposer. A plurality of second passive devices is disposed on the second major surface of the interposer. The second passive devices are different devices than the first passive devices.

An electrical device with a semiconductor circuit that is configured for a high voltage and is arranged in a housing. The housing is formed of a plurality of housing parts which are electrically insulated from one another. Different electrical potentials can be assigned to the housing parts. There is also described an converter with the electrical device.

A method of forming an electrical device is provided that includes forming microprocessor devices on a microprocessor die; forming memory devices on an memory device die; forming component devices on a component die; and forming a plurality of packing devices on a packaging die. Transferring a plurality of each of said microprocessor devices, memory devices, component devices and packaging components to a supporting substrate, wherein the packaging components electrically interconnect the memory devices, component devices and microprocessor devices in individualized groups. Sectioning the supporting substrate to provide said individualized groups of memory devices, component devices and microprocessor devices that are interconnected by a packaging component.