A photonic integrated circuit device includes a semiconductor substrate (e.g., wafer) having a chip region therein, which is bounded on at least one side thereof by a scribe line. The chip region includes an optical transmitter, an optical receiver and a test optical waveguide. This test optical waveguide is coupled to the optical transmitter and the optical receiver and overlaps the scribe line. During a substrate dicing operation, a portion of the test optical waveguide overlapping the scribe line is removed.

Devices, systems, and methods are described related to providing nonlinear lithographic seams, such as rectilinear lithographic seams, between adjacent fields of an integrated circuit die. Such nonlinear lithographic seams include lithographic enabling structures formed in co-planar layers with respect to functional structures in functional units of the fields of the integrated circuit die. Providing nonlinear lithographic seams improves layout efficiency of the functional units of the integrated circuit die.

A method for manufacturing a semiconductor device includes preparing a wafer that includes semiconductor elements, placing the wafer on a stage so that a second electrode is in contact with a place surface of the stage, and measuring an on-resistance of at least one of the semiconductor elements with a first measurement terminal and a second measurement terminal. The on-resistance is measured by contacting the first measurement terminal to a first electrode of one of the semiconductor elements to be measured while applying a control signal to a control electrode of the one of the semiconductor elements, contacting the second measurement terminal to a first electrode of another one of the semiconductor elements while applying the control signal to a control electrode of the another one of the semiconductor elements, and measuring a resistance between the first measurement terminal and the second measurement terminal.

Structures and methods of forming moisture barrier capacitor on a semiconductor component are disclosed. The capacitor is located on the periphery of a semiconductor chip and includes an inner plate electrically connected to a voltage node, an outer plate with fins for electrically connecting to a different voltage node.

An integrated circuit (IC) structure with a single active region having a doping profile different than that of a set of active regions, is disclosed. The IC structure provides a single active region, e.g., a fin, on a substrate with a first doping profile, and a set of active regions, e.g., fins, electrically isolated from the single active region on the substrate. The set of active regions have a second doping profile that is different than the first doping profile of the single active region. For example, the second doping profile can have a deeper penetration into the substrate than the first doping profile.

The invention provides a semiconductor testkey pattern, the semiconductor testkey pattern includes a high density device region and a plurality of resistor pairs surrounding the high density device region, wherein each resistor pair includes two mutually symmetrical resistor patterns.

An integrated circuit (IC) structure with a single active region having a doping profile different than that of a set of active regions, is disclosed. The IC structure provides a single active region, e.g., a fin, on a substrate with a first doping profile, and a set of active regions, e.g., fins, electrically isolated from the single active region on the substrate. The set of active regions have a second doping profile that is different than the first doping profile of the single active region. For example, the second doping profile can have a deeper penetration into the substrate than the first doping profile.

The invention provides a semiconductor testkey pattern, the semiconductor testkey pattern includes a high density device region and a plurality of resistor pairs surrounding the high density device region, wherein each resistor pair includes two mutually symmetrical resistor patterns.

A resistance element includes a conductor, the conductor having a repeating pattern of: a first conductive layer formed on a first interlayer insulating layer on a semiconductor substrate; a second conductive layer formed on a second interlayer insulating layer different from the first interlayer insulating layer; and an interlayer conductive layer connecting the first conductive layer and the second conductive layer, and the second conductive layer has a resistance-value fluctuation characteristic opposite to a resistance-value fluctuation characteristic of the first conductive layer after a heat treatment.

A semiconductor device has a configuration wherein a resistor that restricts overvoltage is inserted between an input terminal and the drain of JFETs, and the resistor is disposed on the JFETs. Also, the resistor is formed contiguously and integrally with a spiral form high breakdown voltage high resistance element that configures a resistive voltage divider circuit.