An electronic device, e.g. integrated circuit, has top and bottom metal plates located over a substrate, the bottom plate located between the top plate and the substrate. A high-stress silicon dioxide layer is located between the bottom plate and the substrate. At least one low-stress silicon dioxide layer is located between the top plate and the bottom plate.

An integrated circuit structure comprises a substrate having a memory region of and an adjacent logic region. A first N type well (Nwell) is formed in the substrate for the memory region and a second Nwell formed in the substrate for the logic region. A plurality of memory transistors in the memory region and a plurality of logic transistors are in the logic region, wherein ones the memory transistors include a floating gate over a channel, and a source and a drain on opposite sides of the channel. A diode portion is formed over one of the source and the drain of at least one of the memory transistors to conduct charge to the floating-gate of the at least one of the memory transistors for state retention during power gating.

A semiconductor substrate has a transistor region, a diode region, and an outer peripheral region. The transistor region is divided into a plurality of transistor unit cell regions by a plurality of gate electrodes each having a stripe shape, and the diode region is divided into a plurality of diode unit cell regions by the plurality of gate electrodes. Each of the plurality of transistor unit cell regions has a third semiconductor layer of a first conductivity type provided on a first main surface side of the semiconductor substrate, a fourth semiconductor layer of a second conductivity type selectively provided on an upper layer part of the third semiconductor layer, and a fifth semiconductor layer. The fifth semiconductor layer is provided to be in contact with an impurity layer of the first conductivity type provided in the outer peripheral region, or to enter the impurity layer.

In one embodiment, an integrated circuit die includes a substrate, a base structure, and a plurality of semiconductor structures. The substrate includes silicon. The base structure is above the substrate and includes one or more group III-nitride (III-N) materials. The semiconductor structures are in a two-dimensional (2D) layout on the base structure and include a plurality of metal contacts, at least some of which have different shapes and comprise different metals.

A transistor package comprising: a substrate; a first transistor in thermal contact with the substrate, wherein the transistor comprises a gate; the substrate sintered to a heat sink through a sintered layer; an encapsulant that at least partially encapsulates the first transistor; and a Kelvin connection to the transistor gate.

A positive-logic FET switch stack that does not require a negative bias voltage, exhibits high isolation and low insertion/mismatch loss, and may withstand high RF voltages. Embodiments include a FET stack comprising series-coupled positive-logic FETs (i.e., FETs not requiring a negative voltage supply to turn OFF), series-coupled on at least one end by an “end-cap” FET of a type that turns OFF when its V.sub.GS is zero volts. The one or more end-cap FETs provide a selectable capacitive DC blocking function or a resistive signal path. Embodiments include a stack of FETs of only the zero V.sub.GS type, or a mix of positive-logic and zero V.sub.GS type FETs with end-cap FETs of the zero V.sub.GS type. Some embodiments withstand high RF voltages by including combinations of series or parallel coupled resistor ladders for the FET gate resistors, drain-source resistors, body charge control resistors, and one or more AC coupling modules.

A semiconductor device, including a semiconductor substrate, a transistor section and a diode section arranged in a predetermined arrangement direction and provided on the semiconductor substrate, is provided. The diode section includes a drift region of a first conductivity-type provided in the semiconductor substrate, a base region of a second conductivity-type extending to a height of an upper surface of the semiconductor substrate and provided above the drift region, first cathode regions of the first conductivity-type, and second and third cathode regions of the second conductivity-type. The first, second, and third cathode regions extend to a height of a lower surface of the semiconductor substrate in a depth direction and provided below the drift region. The first and second cathode regions are provided in contact with each other, alternating in the arrangement direction, and sandwiched between the third cathode regions in an extension direction orthogonal to the arrangement direction.

The present disclosure relates to an integrated chip including a dielectric structure over a substrate. A first capacitor is disposed between sidewalls of the dielectric structure. The first capacitor includes a first electrode between the sidewalls of the dielectric structure and a second electrode between the sidewalls and over the first electrode. A second capacitor is disposed between the sidewalls. The second capacitor includes the second electrode and a third electrode between the sidewalls and over the second electrode. A third capacitor is disposed between the sidewalls. The third capacitor includes the third electrode and a fourth electrode between the sidewalls and over the third electrode. The first capacitor, the second capacitor, and the third capacitor are coupled in parallel by a first contact on a first side of the first capacitor and a second contact on a second side of the first capacitor.

The present disclosure concerns a switching device comprising a first phosphorus-doped silicon layer on top of and in contact with a second arsenic-doped silicon layer. The present disclosure also concerns a method of making a switching device that includes forming a phosphorus-doped silicon layer in an arsenic-doped silicon layer.

Provided is a semiconductor device, comprising: a semiconductor substrate; a transistor portion including an emitter region on the top of the semiconductor substrate; a diode portion including a cathode region on the bottom of the semiconductor substrate and a second conductivity type overlap region in a region other than the cathode region and arranged alongside to the transistor portion a preset arrangement direction on the top of the semiconductor substrate; and an interlayer dielectric film provided between the semiconductor substrate and an emitter electrode and including a contact hole for connecting the emitter electrode and the diode portion. The overlap region is provided to have a first length between the end of the emitter region and the end of the cathode region and a second length, which is shorter than the first length, between the end of the contact hole and the end of the cathode region.