Provided are a semiconductor device and a method for manufacturing same. The device comprises: a substrate, a first insulating layer on the substrate, a plurality of trenches formed in the substrate, a nucleation layer arranged on one side wall of each trench, and a first semiconductor layer formed along the trenches by means of the nucleation layer. The present disclosure facilitates the achievement of one of the following effects: achieving a high height-width ratio and a high integration density, reducing an on-resistance, improving a threshold voltage, achieving a normally-off state, and providing a semiconductor device that has a high power and a high reliability, is suitable for a planarization process, is provided with an easy preparation method, and reduces costs.

Various embodiments of the present disclosure are directed towards an integrated chip a first undoped layer overlies a substrate. A first barrier layer overlies the first undoped layer and has a first thickness. A first doped layer overlies the first barrier layer and is disposed laterally within an n-channel device region of the substrate. A second barrier layer overlies the first barrier layer and is disposed within a p-channel device region that is laterally adjacent to the n-channel device region. The second barrier layer has a second thickness that is greater than the first thickness. A second undoped layer overlies the second barrier layer. A second doped layer overlies the second undoped layer. The second undoped layer and the second doped layer are disposed within the p-channel device region.

The disclosure concerns an electronic device comprising, stacked from a first surface to a second surface, a first stack and a second stack of two high electron mobility transistors, referred to as first and second transistor, the first and the second stack each comprising, from an insulating layer, interposed between the first and the second stack, a barrier layer and a channel layer, the first and the second transistor respectively comprising a first and a second set of electrodes, the first and the second set of electrodes being each provided with a source electrode, with a drain electrode, and with a gate electrode which are arranged so that the first and the second transistor form a half-arm of a bridge.

In an embodiment, a switching circuit is provided that includes a Group III nitride-based semiconductor body including a first monolithically integrated Group III nitride-based transistor device and a second monolithically integrated Group III nitride based transistor device that are coupled to form a half-bridge circuit and are arranged on a common foreign substrate having a common doping level. The switching circuit is configured to operate the half-bridge circuit at a voltage of at least 300 V.

A semiconductor device includes a first and a second nitride-based semiconductor layers, a first and a second electrodes, a first and a second gate electrodes, a first and a second passivation layers and a conductive layer. The first passivation layer has a first portion covered with a first end portion of the first field plate and a second portion free from coverage of the first field plate. The second passivation layer has a first portion covered by the conductive layer and a second portion free from coverage of the conductive layer. A thickness difference between the first and the second portions of the first passivation layer is less than a thickness difference between the first and the second portions of the second passivation layer.

A semiconductor device includes a first and a second nitride-based semiconductor layers, a first and a second electrodes, a first and a second gate electrodes, a first and a second passivation layers and a conductive layer. The first passivation layer has a first portion covered with a first end portion of the first field plate and a second portion free from coverage of the first field plate. The second passivation layer has a first portion covered by the conductive layer and a second portion free from coverage of the conductive layer. A thickness difference between the first and the second portions of the first passivation layer is less than a thickness difference between the first and the second portions of the second passivation layer.

A distributed inductance integrated field effect transistor (FET) structure, comprising a plurality of FETs. Each FET comprises a plurality of source regions, a gate region having a plurality of gate fingers extending from a gate bus bar, a drain region having a plurality of drain finger extending from a drain bus bar between the plurality of gate fingers, wherein the gate region controls current flow in a conductive channel between the drain region and source region. A first distributed inductor connects the gate regions of adjacent ones of the plurality of FETs; and a second distributed inductor connects the drain regions of adjacent ones of the plurality of FETs.

A distributed inductance integrated field effect transistor (FET) structure, comprising a plurality of FETs. Each FET comprises a plurality of source regions, a gate region having a plurality of gate fingers extending from a gate bus bar, a drain region having a plurality of drain finger extending from a drain bus bar between the plurality of gate fingers, wherein the gate region controls current flow in a conductive channel between the drain region and source region. A first distributed inductor connects the gate regions of adjacent ones of the plurality of FETs; and a second distributed inductor connects the drain regions of adjacent ones of the plurality of FETs.

In one embodiment, an integrated circuit die includes a substrate, a base structure, and a plurality of semiconductor structures. The substrate includes silicon. The base structure is above the substrate and includes one or more group III-nitride (III-N) materials. The semiconductor structures are in a two-dimensional (2D) layout on the base structure and include a plurality of metal contacts, at least some of which have different shapes and comprise different metals.

A method for producing a 3D semiconductor device: providing a first level with a first single crystal layer; forming control circuitry of first transistors in and/or on the first level with a first metal layer above; forming a second metal layer above the first metal layer; forming a third metal layer above the second metal layer; forming at least one second level on top of or above the third metal layer; performing additional processing steps to form a plurality of second transistors within the second level; forming a fourth and fifth metal layers above second level; a global power distribution grid includes fifth metal, and local power distribution grid includes the second metal layer, where the fifth metal layer thickness is at least 50% greater than the second metal layer thickness.