A semiconductor capacitor array layout generates parasitic capacitance toward an edge of the layout so as to reduce a capacitance difference between an outer capacitor unit and an inner capacitor unit. The semiconductor capacitor array layout includes a first conductive structure and a second conductive structure. The first conductive structure includes: longitudinal first conductive strips disposed in a first integrated circuit (IC) layer; and lateral first conductive strips disposed in a second IC layer. The longitudinal and lateral first conductive strips jointly form well-type structures including outer wells and inner wells that are electrically connected. The second conductive structure includes second conductors disposed in the first IC layer. The second conductors include outer conductors and inner conductors that are electrically disconnected and respectively disposed in the outer wells and the inner wells. The outer wells and the closest inner conductors jointly generate parasitic capacitance.

A method includes: providing a modulation circuit including a first resistive element, a second resistive element and a third resistive element; providing a memory array and a regulator connecting the modulation circuit to the memory array, wherein the regulator includes a transistor; determining an operation mode of the memory array; generating a first voltage at a drain terminal of the transistor, wherein the first voltage corresponds to a positive, negative zero temperature coefficient according to a first resistance ratio and a second resistance ratio; during a read operation, providing a first driving current to the memory array in response to the first voltage corresponding to the positive temperature coefficient; and during a write operation, providing a second driving current to the memory array in response to the first voltage corresponding to the negative temperature coefficient.

A method includes: providing a modulation circuit and a driving circuit, the modulation circuit configured to generate a temperature-dependent voltage and provide the same to the driving circuit; determined an operation mode of a memory array; providing a first current corresponding to a positive temperature coefficient by the driving circuit in response to the operation mode being a read operation on the memory array; and providing a second current corresponding to a negative temperature coefficient by the driving circuit in response to the operation mode being a write operation on the memory array.

Semiconductor structures and methods of forming the same are provided. A method according to an embodiment includes forming a conductive feature and a first conductive plate over a substrate, conformally depositing a dielectric layer over the conductive feature and the first conductive plate, conformally depositing a conductive layer over the conductive feature and the first conductive plate, and patterning the conductive layer to form a second conductive plate over the first conductive plate and a resistor, the resistor includes a conductive line extending along a sidewall of the conductive feature. By employing the method, a high-resistance resistor may be formed along with a capacitor regardless of the resolution limit of, for example, lithography.

An illustrative device disclosed herein includes a bottom electrode, a conformal switching layer positioned above the bottom electrode and a top electrode positioned above the conformal switching layer. The top electrode includes a conformal layer of conductive material positioned above the conformal switching layer and a conductive material positioned above the conformal layer of conductive material.

A method of forming circuitry components includes forming a stack of horizontally extending and vertically overlapping features. The features extend horizontally though a primary portion of the stack with at least some of the features extending farther in the horizontal direction in an end portion. Operative structures are formed vertically through the features in the primary portion and dummy structures are formed vertically through the features in the end portion. Openings are formed through the features to form horizontally elongated and vertically overlapping lines from material of the features. The lines individually extend laterally about sides of vertically extending portions of both the operative structures and the dummy structures. Sacrificial material that is elevationally between the lines is at least partially removed in the primary and end portions laterally between the openings. Other aspects and implementations are disclosed.

A method of forming an array of memory cells comprises forming an elevationally inner tier of memory cells comprising spaced inner tier lower first conductive lines, spaced inner tier upper second conductive lines, and programmable material of individual inner tier memory cells elevationally between the inner tier first lines and the inner tier second lines where such cross. First insulative material is formed laterally between the inner tier second lines to have respective elevationally outermost surfaces that are lower than elevationally outermost surfaces of immediately laterally-adjacent of the inner tier second lines. Second insulative material is formed elevationally over the first insulative material and laterally between the inner tier second lines. The second insulative material is of different composition from that of the first insulative material. An elevationally outer tier of memory cells is formed to comprise spaced outer tier lower first conductive lines, spaced outer tier upper second conductive lines, and programmable material of individual outer tier memory cells elevationally between the outer tier first lines and the outer tier second lines where such cross. Arrays of memory cells independent of method of manufacture are disclosed.

A method of forming circuitry components includes forming a stack of horizontally extending and vertically overlapping features. The features extend horizontally though a primary portion of the stack with at least some of the features extending farther in the horizontal direction in an end portion. Operative structures are formed vertically through the features in the primary portion and dummy structures are formed vertically through the features in the end portion. Openings are formed through the features to form horizontally elongated and vertically overlapping lines from material of the features. The lines individually extend laterally about sides of vertically extending portions of both the operative structures and the dummy structures. Sacrificial material that is elevationally between the lines is at least partially removed in the primary and end portions laterally between the openings. Other aspects and implementations are disclosed.

Some embodiments include a memory device having first structures arranged in a first direction and second structures arranged in a second direction. At least one structure among the first and second structures includes a semiconductor material. The second structures contact the first structures at contact locations. A region at each of the contact locations is configured as memory element to store information based on a resistance of the region. The structures can include nanowires. Other embodiments are described.

Memory devices and memory operational methods are described. One example memory system includes a common conductor and a plurality of memory cells coupled with the common conductor. The memory system additionally includes access circuitry configured to provide different ones of the memory cells into one of a plurality of different memory states at a plurality of different moments in time between first and second moments in time. The access circuitry is further configured to maintain the common conductor at a voltage potential, which corresponds to the one memory state, between the first and second moments in time to provide the memory cells into the one memory state.