Exemplary methods of etching may include flowing a fluorine-containing precursor and a secondary gas into a processing region of a semiconductor processing chamber. The secondary gas may be or include oxygen or nitrogen. A flow rate ratio of the fluorine-containing precursor to the secondary gas may be greater than or about 1:1. The methods may include contacting a substrate with the fluorine-containing precursor and the secondary gas. The substrate may include an exposed metal. The substrate may define a high aspect-ratio structure. The methods may include etching the exposed metal within the high aspect-ratio structure.

A ferroelectric component includes a first electrode, a tunnel barrier layer disposed on the first electrode to include a ferroelectric material, a tunneling control layer disposed on the tunnel barrier layer to control a tunneling width of electric charges passing through the tunnel barrier layer, and a second electrode disposed on the tunneling control layer.

A transistor device includes a transistor and programmable controller. The controller has an output that controls operation of the transistor. The controller includes analog computing circuitry and optionally digital computing circuitry that may be used to setup the analog computing circuitry. In addition to two connectors for connecting the transistor into an external circuit, the device includes a further connector that provides an input to the controller and through which the control can be programmed post manufacture. The transistor device may be a discrete component in which transistor and controlling circuitry are held in packaging, the three connectors exposed through the packaging in order to connect the device to an external circuit.

A memory device includes at least one semiconductor layer having a double PN junction, and an anode and a cathode which simultaneously contact the semiconductor layer, wherein a junction between the semiconductor layer and the anode is a Schottky junction, and a junction between the semiconductor layer and the cathode is an Ohmic junction. In addition, a capacitor-less memory device includes at least one semiconductor layer including a double PN junction, a control gate which contacts the semiconductor layer, and an anode and a cathode which simultaneously contact the semiconductor layer, wherein a junction between the semiconductor layer and the anode is a Schottky junction, and a junction between the semiconductor layer and the cathode is an Ohmic junction. Methods of operating the memory device and the capacitor-less memory device are also disclosed.

A semiconductor device includes a first conductive line and a second conductive line spaced apart from the first conductive line. A semiconductor pattern is disposed between the first conductive line and the second conductive line. The semiconductor pattern includes a first semiconductor pattern having first-conductivity-type impurities disposed adjacent to the first conductive line. A second semiconductor pattern having second-conductivity-type impurities is disposed adjacent to the second conductive line. A third semiconductor pattern is disposed between the first semiconductor pattern and the second semiconductor pattern. The third semiconductor pattern includes a first region disposed adjacent to the first semiconductor pattern and a second region disposed between the first region and the second semiconductor pattern. At least one of the first region and the second region comprises an intrinsic semiconductor layer. A first gate line crosses the first region and a second gate line crosses the second region.

A product-sum calculation with high power efficiency is performed while maintaining a small area of a memory cell. A semiconductor device includes a memory cell array in which a plurality of memory cells is arranged in a matrix. Then, each memory cell of the plurality of memory cells includes a flip-flop circuit including two inverter circuits in each of which a load field effect transistor and a drive field effect transistor are connected in series, input portions and output portions of the two inverter circuits being cross-joined to each other, two transfer field effect transistors each having a gate electrode connected to a word line, and a pair of first and second main electrode regions, the first main electrode regions being respectively connected to the output portions of the two inverter circuits, and two resistance elements of which one end sides are respectively connected to the second main electrode regions of the two transfer field effect transistors and other end sides are respectively connected to a bit line and a bit line bar.

A vertical thyristor memory array including: a vertical thyristor memory cell, the vertical thyristor memory cell including: a p+ anode; an n-base located below the p+ anode; a p-base located below the n-base; a n+ cathode located below the p-base; an isolation trench located around the vertical thyristor memory cell; an assist gate located in the isolation trench adjacent the n-base wherein an entire vertical height of the assist gate is positioned within an entire vertical height of the n-base.

Provided are a neuromorphic device and a neuromorphic circuit using the neuromorphic device. The neuromorphic device is configured to include a first semiconductor region formed on a substrate in a wall shape or a dumbbell shape; first, second, third, and fourth doped regions sequentially formed in the first semiconductor region; first and second gate insulating film stacks disposed on the respective side surfaces of the second doped region; first and second gate electrodes respectively disposed on the respective side surfaces of the second doped region; the first and second gate electrodes disposed on the respective side surface of the second doped region, the first and second gate electrodes being electrically insulated from the second doped, region by the first and second gate insulating film stacks; and first and second electrodes electrically connected to the first and fourth doped regions, respectively.

A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states. A first region of the memory cell is in electrical contact with the floating body region. A second region of the memory cell is spaced apart from the first region and is also in electrical contact with the floating body region. A gate is positioned between the first and second regions. A back-bias region is configured to generate impact ionization when the memory cell is in one of the first and second states, and the back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of the first and second states.

A memory device, an operating method of the memory device, and a fabricating method of the memory device are provided. A memory device includes: a semiconductor column extending vertically on a substrate and including a source region of a first conductivity type, an intrinsic region, and a drain region of a second conductivity type; a first gate electrode disposed adjacent to the drain region to cover the intrinsic region; a second gate electrode spaced apart from the first gate electrode and disposed adjacent to the source region to cover the intrinsic region; a first gate electrode disposed between the first gate electrode and the intrinsic region; and a second gate insulating layer disposed between the second gate electrode and the intrinsic region.