To provide a display device capable of displaying a plurality of images by superimposition using a plurality of memory circuits provided in a pixel. A plurality of memory circuits are provided in a pixel, and signals corresponding to images for superimposition are retained in each of the plurality of memory circuits. In the pixel, the signals corresponding to the images for superimposition are added to each of the plurality of memory circuits. The signals are added to the signals retained in the memory circuits by capacitive coupling. A display element can display an image corresponding to a signal in which a signal written to a pixel through a wiring is added to the signals retained in the plurality of memory circuits. Reduction in the amount of arithmetic processing for displaying images by superimposition can be achieved.

A semiconductor device that can perform product-sum operation with low power is provided. The semiconductor device includes a switching circuit. The switching circuit includes first to fourth terminals. The switching circuit has a function of selecting one of the third terminal and the fourth terminal as electrical connection destination of the first terminal, and selecting the other of the third terminal and the fourth terminal as electrical connection destination of the second terminal, on the basis of first data. The switching circuit includes a first transistor and a second transistor each having a back gate. The switching circuit has a function of determining a signal-transmission speed between the first terminal and one of the third terminal and the fourth terminal and a signal-transmission speed between the second terminal and the other of the third terminal and the fourth terminal on the basis of potentials of the back gates. The potentials are determined by second data. When signals are input to the first terminal and the second terminal, a time lag between the signals output from the third terminal and the fourth terminal is determined by the first data and the second data.

To provide an inexpensive display device. The display device includes a pixel and an IC chip. The pixel includes a first pixel circuit including a display element and a second pixel circuit including a light-receiving device. The one IC chip includes a control circuit, a data driver circuit, and a read circuit. The first and second pixel circuits are electrically connected to the read circuit. The control circuit has a function of controlling driving of the data driver circuit and the read circuit. The data driver circuit has a function of supplying image data to the first pixel circuit. The read circuit has a function of outputting a monitor signal corresponding to a monitor current when the monitor current flows through the first pixel circuit. The read circuit also has a function of outputting an imaging signal corresponding to imaging data acquired by the second pixel circuit.

A novel information processing device with least signal transmission delay and low power consumption is provided. A storage device includes a first layer, a second layer, and a third layer. The first layer is provided with a circuit. The second layer is provided with a memory cell portion. The third layer is provided with a first electrode. The circuit has a function of switching and performing reading or writing of first data or second data from or to the memory cell portion. At least part of the second layer is stacked above the first layer. At least part of the third layer is stacked above the second layer. An arithmetic device includes a fourth layer and a fifth layer. The fourth layer is provided with a central processing device. The fifth layer is provided with a second electrode. At least part of the fifth layer is stacked above the fourth layer. The circuit is electrically connected to the central processing device through the first electrode and the second electrode.

An integrated circuit having a transistor architecture includes a first semiconductor body and a second semiconductor body. The first and second semiconductor bodies are arranged vertically (e.g., stacked configuration) or horizontally (e.g., forksheet configuration) with respect to each other, and separated from one another by insulator material, and each can be configured for planar or non-planar transistor topology. A first gate structure is on the first semiconductor body, and includes a first gate electrode and a first high-k gate dielectric. A second gate structure is on the second semiconductor body, and includes a second gate electrode and a second high-k gate dielectric. In an example, the first gate electrode includes a layer comprising a compound of silicon and one or more metals; the second gate structure may include a silicide workfunction layer, or not. In one example, the first gate electrode is n-type, and the second gate electrode is p-type.

Gallium nitride (GaN) layer transfer for integrated circuit technology is described. In an example, an integrated circuit structure includes a substrate including silicon. A first layer including gallium and nitrogen is over a first region of the substrate, the first layer having a gallium-polar orientation with a top crystal plane consisting of a gallium face. A second layer including gallium and nitrogen is over a second region of the substrate, the second layer having a nitrogen-polar orientation with a top crystal plane consisting of a nitrogen face.

An RF MOSFET includes respective pluralities of gate fingers, source fingers, and drain fingers formed on a semiconductor structure. The gate fingers are spaced apart from each other along a first direction, extend in a second, orthogonal direction, and are electrically connected to one another through a gate mandrel. The source fingers are spaced apart from each other along the first direction, extend in the second direction, and are electrically connected to one another through a source mandrel. The drain fingers are spaced apart from each other along the first direction, extend in the second direction, and are electrically connected to one another through a drain mandrel. Adjacent unit cell transistors of the RF MOSFET are separated from one another by a dummy gate and a trench that extends into the semiconductor structure. The semiconductor structure may be a bulk semiconductor wafer, a PD-SOI wafer, or an FD-SOI wafer.

A sensor system with a first semiconductor die part and with a second semiconductor die part is proposed, wherein the first semiconductor die part has a microelectromechanical sensor element, wherein the second semiconductor die part covers the microelectromechanical sensor element, wherein the second semiconductor die part has a via for electrically contacting the microelectromechanical sensor element, in particular directly. A method for producing a sensor system is also proposed.

An imaging device capable of taking an image in both a dark environment and a bright environment in a light amount range equivalent to or greater than that of human vision is desired. A wide dynamic range and high image quality are achieved. In order to obtain an image with a widened dynamic range, two capacitors, a large capacitor and a small capacitor, are provided in one pixel. The large capacitor is formed to be interposed between a transistor for controlling the amount of charge overflowed from the small capacitor and a transistor for resetting accumulated charge, and OS transistors are used as these two transistors. The OS transistor has extremely low off-state current characteristics, and thus can widen the dynamic range of imaging.

A memory device with large storage capacity is provided. A NAND memory device includes a plurality of connected memory cells each provided with a writing transistor, a reading transistor, and a capacitor. An oxide semiconductor is used in a semiconductor layer of the writing transistor. The reading transistor includes a back gate. When a reading voltage is applied to the back gate, information stored in the memory cell is read out.