An array substrate, a method for manufacturing an array substrate, and a display panel are provided. The array substrate includes a substrate and a thin film transistor layer arranged on the substrate. The thin film transistor layer includes a plurality of thin film transistors. The thin film transistors each include an active layer, a source/drain, a first gate, a second gate, and a first insulating layer. The first gate and the second gate are electrically connected through the through hole. The problems of difficulty in etching and excessively long etching time are avoided while reducing the gate resistance of the thin film transistor.

Embodiments of the disclosure relate to a display panel and a display device. Specifically, there may be provided a display panel and display device capable of simplifying the process, by comprising a substrate, first to fourth signal lines and an active layer disposed on the substrate, a first metal layer and a second metal layer disposed on a portion of an upper surface of the active layer and spaced apart from each other, a first insulation film disposed on the first and second metal layers, a second insulation film disposed on the first insulation film, an electrode pattern disposed on the active layer and the first insulation film and not overlapping the second insulation film, and a fifth signal line disposed on the second insulation film and crossing the first to fourth signal lines spaced apart from each other, wherein the first electrode contacts an upper surface of the first metal layer disposed on the active layer, and wherein the fifth signal line is disposed on the same layer as the first electrode.

According to an aspect of the present disclosure, a liquid crystal display device includes a lower substrate including a black matrix and a color filter; an upper substrate disposed to be opposite to the lower substrate; a thin film transistor which on the upper substrate to be opposite to the color filter, and including a gate electrode, an active layer, a source electrode, and a drain electrode; at least one insulting layer disposed on the thin film transistor; a pixel electrode disposed on the insulating layer and electrically connected to the drain electrode; and a common electrode spaced apart from the pixel electrode, and the gate electrode includes a first gate conductive layer including a transparent conductive material, a second gate conductive layer including a first transition metal oxide and a second transition metal oxide, and a third gate conductive layer formed of an opaque conductive layer.

A highly reliable semiconductor device is provided. A second insulating layer is positioned over a first insulating layer. A semiconductor layer is positioned between the first insulating layer and the second insulating layer. A third insulating layer is positioned over the second insulating layer. A fourth insulating layer is positioned over the third insulating layer. A first conductive layer includes a region overlapping with the semiconductor layer, and is positioned between the third insulating layer and the fourth insulating layer. The third insulating layer includes a region in contact with a bottom surface of the first conductive layer and a region in contact with the fourth insulating layer. The fourth insulating layer is in contact with a top surface and a side surface of the first conductive layer. A fifth insulating layer is in contact with a top surface and a side surface of the semiconductor layer. The fifth insulating layer includes a first opening and a second opening in a region overlapping with the semiconductor layer and not overlapping with the first conductive layer. A second conductive layer and a third conductive layer are electrically connected to the semiconductor layer in the first opening and the second opening, respectively. The third to fifth insulating layers include metal, and oxygen or nitrogen. A sixth insulating layer includes a region in contact with a top surface and a side surface of the fifth insulating layer and a region in contact with the first insulating layer.

The present invention is equipped with: a substrate (10) that has a surface upon which a drive circuit containing a TFT (20) is formed; a planarization film (30) that makes the surface of the substrate planar by covering the drive circuit; and an organic light-emitting element (40) that is provided with a first electrode (41) formed upon the surface of the planarization film and connected to the drive circuit, an organic light-emitting layer (43) formed upon the first electrode, and a second electrode (44) formed upon the organic light-emitting layer. In addition, the planarization film has a two-layer structure comprising an inorganic insulating film (31) and an organic insulating film (32) that are layered upon the TFT, a conductor layer containing a titanium layer and a copper layer is embedded in the interior of a contact hole, and the first electrode is formed electrically connected to the conductor layer.

An active matrix substrate includes a plurality of source bus lines, a lower insulating layer covering the source bus lines, a plurality of gate bus lines formed above the lower insulating layer, and an oxide semiconductor TFT disposed to correspond to each pixel area. The oxide semiconductor TFT includes an oxide semiconductor layer disposed on the lower insulating layer, and a gate electrode disposed above the oxide semiconductor layer. The gate electrode is formed in a different layer from the gate bus lines, and is disposed to be separated from another gate electrode disposed in an adjacent pixel area. The gate electrode is covered by an interlayer insulating layer. The gate bus line is disposed on the interlayer insulating layer and in a gate contact hole formed in the interlayer insulating layer, and is connected to the gate electrode in the gate contact hole.

A display device includes a first pixel, a second pixel disposed adjacent to the first pixel, and a recess pattern traversing between the first pixel and the second pixel when viewed from top. Each of the first pixel and the second pixel includes a first supply voltage line, a light-emitting element, a first transistor connected between the first supply voltage line and the light-emitting element, a second transistor connected between the first transistor and the light-emitting element, and a third transistor connected to the light-emitting element. The display device further includes a first semiconductor layer defining a channel of each of the first transistor, the second transistor, and the third transistor. The second transistor of the first pixel is connected to the third transistor of the second pixel via the first semiconductor layer. The first semiconductor layer overlaps the recess pattern between the first pixel and the second pixel.

A display device includes a first light blocking layer disposed on a substrate, a second light blocking layer disposed on the substrate and spaced apart from the first light blocking layer, an active layer including a first area disposed on the first light blocking layer, a second area disposed on the substrate between the first light blocking layer and the second light blocking layer, and a third area disposed between the first area and the second area, a gate electrode disposed on the active layer and overlapping a portion of the first area, a first electrode disposed on the gate electrode, and including at least a portion overlapping the first light blocking layer, and a second electrode disposed on the gate electrode, and including at least a portion overlapping the second light blocking layer and at least another portion overlapping the third area of the active layer.

A display device includes a first base layer including a first opening; a first barrier layer located on a surface of the first base layer, and including a second opening; and a pad electrode located on the first barrier layer and overlapping the second opening in a plan view. At least one first groove is formed at a surface of the first barrier layer, a second groove is formed at a surface of the pad electrode, and the first opening exposes the at least one first groove and the second groove.

The present disclosure provides a piezoelectric sensor, a pressure detecting device, their manufacturing methods and a detection method. The piezoelectric sensor comprises a thin film transistor located on a substrate and comprising an active layer, and a piezoelectric layer that is in contact with the active layer of the thin film transistor.