As a display device has a higher definition, the number of pixels, gate lines, and signal lines are increased. When the number of the gate lines and the signal lines are increased, a problem of high manufacturing cost, because it is difficult to mount an IC chip including a driver circuit for driving of the gate and signal lines by bonding or the like. A pixel portion and a driver circuit for driving the pixel portion are provided over the same substrate, and at least part of the driver circuit includes a thin film transistor using an oxide semiconductor interposed between gate electrodes provided above and below the oxide semiconductor. Therefore, when the pixel portion and the driver portion are provided over the same substrate, manufacturing cost can be reduced.

An array substrate structure is provided, which includes a substrate with a first surface and a second surface opposite to the first surface. A first TFT is on the first surface of the substrate, and a second TFT is on the second surface of the substrate. A through via passes through the substrate, and the first TFT is electrically connected to the second TFT through the through via.

A display device is disclosed. The display device includes a display area and a wiring area. The display area is disposed with a first thin film transistor which is an oxide thin film transistor and a second thin film transistor which is a low temperature poly-silicon thin film transistor. A distance between a first active layer of the first thin film transistor and a substrate is different from a distance between a second active layer of the second thin film transistor and the substrate. The first thin film transistor includes first vias that receive a first source/drain. The second thin film transistor includes second vias that receives a second source/drain. The wiring area is provided with a groove. The groove includes a first sub-groove and a second sub-groove that are stacked, and depths of the second vias are substantially equal to a depth of the second sub-groove.

A display panel includes a substrate, a first thin film transistor including a first semiconductor layer and a first gate electrode, a data line extending in a first direction, a scan line extending in a second direction, a second thin film transistor electrically connected to the data line and including a second semiconductor layer and a second gate electrode, a third thin film transistor including a third semiconductor layer and a first upper gate electrode arranged on the third semiconductor layer, a node connection line electrically connecting the first thin film transistor and the third thin film transistor, and a shield line located between the data line and the node connection line in a plan view and including the same material as the first upper gate electrode of the third thin film transistor. The first semiconductor layer includes a silicon semiconductor, and the third semiconductor layer includes an oxide semiconductor.

An organic light-emitting display apparatus includes an organic light-emitting diode, a switching transistor, a first light emission control transistor, and a driving transistor. The organic light-emitting diode includes an anode and a cathode for receiving a reference voltage. The switching transistor includes a gate electrode for receiving an nth scan signal and a source electrode for receiving a data signal, and is an NMOS transistor. The first light emission control transistor includes a gate electrode for receiving a light emission control signal, and is configured to turn on upon receiving the light emission control signal to determine a timing of flow of a driving current to the organic light-emitting diode, and is a PMOS transistor. The driving transistor is connected to the switching transistor and the first light emission control transistor and provides the driving current to the organic light-emitting diode.

A memory device having long data retention time and high reliability is provided. The memory device includes a driver circuit and a plurality of memory cells, the memory cell includes a transistor and a capacitor, and the transistor includes a metal oxide in a channel formation region. The transistor includes a first gate and a second gate, and in a period during which the memory cell retains data, negative potentials are applied to the first gate and the second gate of the transistor.

Disclosed are a display substrate, a manufacturing method thereof, a display panel and a display device. The display panel comprises: a base substrate provided with a first area and a second area which are not overlapped with each other; a low temperature poly-silicon transistor arranged in the first area, the low temperature poly-silicon transistor comprises a poly-silicon active layer; an oxide transistor arranged in the second area, the oxide transistor comprises a first gate electrode; the first gate electrode is arranged in a same layer as the poly-silicon active layer, and a material of the first gate electrode is heavily-doped poly-silicon.

A pixel includes a light emitting element, a driving switching element and a first compensation switching element and a second compensation switching element. The driving switching element is which applies a driving current to the light emitting element. The first compensation switching element and the second compensation switching element are connected between a control electrode of the driving switching element and an output electrode of the driving switching element. The first compensation switching element and the second compensation switching element are connected to each other in series. The driving switching element is a P-type transistor. The first compensation switching element is an N-type transistor. The second compensation switching element is a P-type transistor.

A display device includes a substrate, a first electrode disposed on the substrate, a second electrode disposed on the substrate and spaced apart from the first electrode, a plurality of first protruding electrodes disposed on the first electrode, a plurality of second protruding electrodes disposed on the second electrode, and a plurality of light emitting elements electrically connected to the plurality of first protruding electrodes and the plurality of second protruding electrodes.

First to fourth switches are provided so that conduction states are able to be controlled independently of each other. The first switch, the third switch, and the second switch are electrically connected in series between a first wiring and a third wiring. The fourth switch has a function of controlling a conduction state between the light-emitting element and a fourth wiring. In a first transistor, a gate is electrically connected to a node to which the third switch and the second switch are electrically connected, one of a source and a drain is electrically connected to a second wiring, and the other is electrically connected to the light-emitting element. A capacitor includes first and second electrodes, the first electrode is electrically connected to a node to which the first switch and the third switch are electrically connected, and the second electrode is electrically connected to the light-emitting element.